Principal Engineer, Automated Derivatives

Renesas Electronics; Austin (TX); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics seeks a senior leader to drive end-to-end derivative SoCs, integrating RTL design with AI-augmented verification and physical implementation.

You will push rapid convergence by predicting timing, optimizing logic, and enabling zero-friction RTL-to-PD handoffs while leveraging ML to reuse placements across derivatives.

Qualifications

• Master’s degree required in a relevant field.
• 12–15 years of professional semiconductor industry experience.
• Expertise in SystemVerilog for RTL and UVM for verification.
• Proficiency with AI/ML integration in EDA/tooling is advantageous.

Responsibilities

• Lead AI-augmented RTL architectures and derivatives, driving efficient timelines.
• Develop automated testbenches and smart regression strategies to cut compute time.
• Accelerate physical implementation with zero-friction RTL-to-PD handoffs and reuse approaches.

Skills

SystemVerilog

UVM

Python

Tcl/Python

Git

CI/CD

Jenkins

GitLab

Synthesis

P&R

STA

VCS

Xcelium

Innovus

ICC2

Education

Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

VCS

Xcelium

Innovus

ICC2

Git

Jenkins

GitLab

Job description

In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs, focusing on intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants.

Key Responsibilities

1. AI-Augmented RTL & Architecture

• Physical-Aware RTL: Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations.
• Derivative Generation: Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants.
• Logic Optimization: Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs.
• Automated Testbench Scaling: Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated.
• Smart Regression Management: Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs.
• Bug Prediction: Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data.

3. Rapid Physical Implementation

• Seamless Handoff: Ensure a "zero-friction" path from RTL to Physical Design by using AI to automatically generate floorplan constraints and timing assertions from the design spec.
• Closure Acceleration: Drive the physical implementation of derivatives, using AI to "reuse" placement and routing solutions from parent designs to achieve 10x faster convergence.

Job Description

In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs, focusing on intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants.

Key Responsibilities

1. AI-Augmented RTL & Architecture

• Physical-Aware RTL: Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations.
• Derivative Generation: Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants.
• Logic Optimization: Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs.

2. Intelligent Verification

• Automated Testbench Scaling: Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated.
• Smart Regression Management: Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs.
• Bug Prediction: Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data.

3. Rapid Physical Implementation

• Seamless Handoff: Ensure a "zero-friction" path from RTL to Physical Design by using AI to automatically generate floorplan constraints and timing assertions from the design spec.
• Closure Acceleration: Drive the physical implementation of derivatives, using AI to "reuse" placement and routing solutions from parent designs to achieve 10x faster convergence.

Qualifications

• Education: Minimum of a Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
• Experience: 12–15 years of professional experience in the semiconductor industry, with a focus on:
  • Full-Stack Hardware Mastery: Proficiency in SystemVerilog for RTL design and UVM for functional verification.
  • Physical Design Foundation: Solid understanding of Synthesis, P&R, and STA (Static Timing Analysis) to ensure RTL is physically realisable.
  • ML/AI Integration: Expert Python skills to build and deploy models that interface with both simulation tools (VCS, Xcelium) and implementation tools (Innovus, ICC2).
  • Data-Driven Flow Dev: Experience using Tcl/Python to extract "features" from simulation logs and implementation reports to train predictive models.
  • Version Control & CI/CD: Mastery of Git and CI/CD pipelines (Jenkins/GitLab) to manage the high-velocity deployment of design derivatives.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.