Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

InvestedintheMission; Sunnyvale (CA); On-site; USD 175,000 - 280,000; Full time

Job summary

SpaceX is recruiting a Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) to join the Starlink initiative.

You will develop cutting-edge silicon for space and ground infrastructure, collaborating with cross-disciplinary teams to push the envelope of performance and reliability. The role demands deep experience in ASIC/physical design flows, RTL2GDSII signoff, and strong scripting skills, with a willingness to work extended hours to meet critical milestones.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 5+ years of ASIC or physical design flow development experience.
• Strong collaboration with cross-disciplinary teams.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
• Develop/improve physical design methodologies and automation scripts for various implementation steps.
• Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in STA, noise, logic equivalency, physical verification, electromigration and voltage drop.

Skills

ASIC design

Physical design

RTL2GDSII

Scripting

Team collaboration

Education

Bachelor's degree in electrical/computer engineering or computer science

Tools

EDA tools

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
• Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of its impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:
Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affiative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].