Sr. Radar Perception Engineer - 3D Obstacle & Sensor Fusion

NVIDIA Corporation

Santa Clara, Northern (CA, KY)

Hybrid

USD 224,000 - 357,000

Full time

10 days ago

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Job summary

NVIDIA Corporation is seeking an exceptional Senior Radar Perception Engineer to architect and productize a next‑generation autonomous driving radar perception stack. Lead 3D radar perception, multi‑sensor fusion, and production‑grade DL models with CUDA optimizations.

This role demands deep expertise in radar signal processing, transformer models, and end‑to‑end deployment at scale. You will collaborate across AI, hardware, and safety teams to define architectures, drive performance, and push

Qualifications

  • 12+ years of hands-on deep learning perception or radar systems experience.
  • Proficiency in PyTorch; production-grade software exposure.
  • Strong Python and C++ programming for high-performance software.
  • Excellent cross-functional collaboration across AI, hardware, safety.
  • BS/MS/PhD in CS/EE/Robotics or equivalent experience.

Responsibilities

  • Develop radar-based 3D obstacle perception architectures and roadmaps.
  • Research deep learning models to improve radar point cloud representations.
  • Design fusion with camera, radar, and lidar for BEV understanding.
  • Drive radar sensor evaluation and multi-sensor stack integration.
  • Define KPI frameworks and perform large-scale data analysis.

Skills

Radar perception
PyTorch
Python/C++
Cross-functional collaboration

Education

BS/MS/PhD in CS/EE/Robotics

Tools

CUDA
Transformers
PyTorch

Job description

NVIDIA Corporation is seeking an exceptional Senior Radar Perception Engineer to architect and productize a next‑generation autonomous driving radar perception stack. Lead 3D radar perception, multi‑sensor fusion, and production‑grade DL models with CUDA optimizations.

This role demands deep expertise in radar signal processing, transformer models, and end‑to‑end deployment at scale. You will collaborate across AI, hardware, and safety teams to define architectures, drive performance, and push

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