Sr. Engineer, Infrastructure PBC Layout

ADP, Inc.

Santa Clara (CA)

On-site

USD 125,000 - 172,000

Full time

11 days ago
Application generator

A complete application in a minute — tailored resume and cover letter, ready to send.

Get past ATS filters

Benefits offered by this job

401k plan
Health and wellness benefits
Parental leave
Equity grants

Job summary

SiTime is the Precision Timing company in Santa Clara, CA. We seek a hands-on Senior PCB Layout Engineer to own the physical implementation of complex PCBs used in characterization, validation, automated test equipment, production test, and internal engineering platforms.

The ideal candidate brings 10+ years of practical layout experience and a proven record of releasing high-quality boards from placement through fabrication and assembly.

Qualifications

  • 10+ years hands-on PCB layout experience for complex, high-density electronic systems.
  • Expert-level capability in at least one major PCB layout platform, Cadence Allegro or Altium Designer.
  • Demonstrated experience laying out multi-layer high-speed digital, mixed-signal, RF, and power designs.
  • Strong knowledge of stack-ups, controlled impedance, differential routing, crosstalk mitigation, grounding, and PI fundamentals.
  • Experience with fine-pitch BGAs, HDI, microvias, via-in-pad, blind/buried vias.
  • Ability to interpret schematics, mechanical drawings, PCB specifications, and constraint documents.

Responsibilities

  • Own PCB layout from initial placement and routing through design review and fabrication release.
  • Translate schematics, mechanical requirements, stack-ups, and electrical constraints into complete board layouts.
  • Route dense mixed-signal, high-speed digital, precision analog, RF, clock, power, and control circuitry.
  • Create and maintain fabrication and assembly deliverables (Gerber/ODB++, drill files, drawings, pick-and-place files).
  • Perform design-rule checks and release-package reviews for data accuracy and completeness.

Skills

PCB layout
Cadence Allegro
Altium Designer
HDI
microvias
via-in-pad
differential routing
power integrity
RF design
fine-pitch BGA

Education

Bachelor's degree in electronics

Tools

Cadence Allegro
Altium Designer

Job description

If you are unable to complete this application due to a disability, contact this employer to ask for an accommodation or an alternative application process.

Full-time Regular Santa Clara, CA, US

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary
  • We are seeking a hands-on Senior PCB Layout Engineer to own the physical implementation of complex printed circuit boards used in characterization, validation, automated test equipment (ATE), production test, and internal engineering platforms. This role partners closely with hardware, signal integrity, mechanical, manufacturing, and test engineers to translate schematics and design constraints into robust, manufacturable PCB layouts. The ideal candidate brings at least 10 years of practical layout experience, strong design judgment, and a proven record of releasing high-quality boards from placement through fabrication and assembly.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:
PCB Placement, Routing, and Release Ownership
  • Own PCB layout from initial placement and routing through design review, fabrication release, assembly support, and post-build updates
  • Translate schematics, mechanical requirements, stack-ups, and electrical constraints into complete board layouts
  • Route dense mixed-signal, high-speed digital, precision analog, RF, clock, power, and control circuitry.
  • Create and maintain fabrication and assembly deliverables, including Gerber or ODB++ data, drill files, drawings, pick-and-place files, and manufacturing notes
  • Perform thorough design-rule checks and release-package reviews to ensure data accuracy and completeness
Constraint Management and Design Quality
  • Implement controlled-impedance routing, differential pairs, length matching, return-path continuity, isolation, shielding, grounding, and power-distribution requirements
  • Collaborate with electrical and SI/PI engineers to apply routing constraints and incorporate simulation or review feedback
  • Develop practical placement and routing strategies for high-density interconnect, fine-pitch BGA, via-in-pad, blind and buried vias, and other advanced PCB technologies
  • Maintain component footprints, padstacks, symbols, and library data in accordance with IPC guidance and company standards
  • Conduct peer reviews and contribute to PCB layout checklists, standards, templates, and reusable design practices
Manufacturing and Cross-Functional Execution
  • Drive DFM, DFA, and DFT reviews with PCB fabrication, assembly, test, and supply-chain partners
  • Resolve fabrication and assembly questions, document deviations, and incorporate lessons learned into future layouts
  • Work closely with mechanical engineers on board outlines, component clearances, keep-outs, connector locations, thermal constraints, and enclosure integration
  • Support prototype bring-up and root-cause analysis by reviewing layout-related signal, power, thermal, assembly, and reliability issues
  • Communicate design status, trade-offs, risks, and release readiness clearly to project stakeholders
Qualifications & Requirements (Education must be included):
  • 10+ years of hands-on PCB layout experience for complex, high-density electronic systems
  • Expert-level capability in at least one major PCB layout platform, such as Cadence Allegro, Altium Designer, and working familiarity across common PCB design and review tools
  • Demonstrated experience laying out multi-layer high-speed digital, mixed-signal, precision analog, RF, clock, and power designs
  • Strong knowledge of PCB stack-ups, materials, controlled impedance, differential routing, length matching, crosstalk mitigation, return paths, grounding, and power integrity fundamentals
  • Experience with fine-pitch BGAs, HDI, microvias, via-in-pad, blind/buried vias
  • Practical knowledge of PCB fabrication, assembly processes, component land patterns, solder-mask and paste-mask design, panelization, tolerances, and manufacturing documentation
  • Experience applying DFM, DFA, and DFT principles and working directly with fabrication and assembly suppliers
  • Ability to interpret schematics, mechanical drawings, PCB specifications, component datasheets, and constraint documents
  • Strong attention to detail, configuration discipline, and ability to manage multiple board releases and design revisions
  • Clear written and verbal communication skills and the ability to work effectively across engineering and manufacturing teams
Desired Characteristics & Attributes:
  • Bachelor’s degree, technical certification, or equivalent practical experience in electronics, electrical engineering, PCB design, or a related field
  • Experience with boards used for semiconductor characterization, validation, ATE, production test, probe, or laboratory instrumentation
  • Familiarity with SI/PI review or simulation tools and the ability to interpret analysis results and implement layout changes
  • Knowledge of IPC-2221, IPC-7351, IPC-6012, IPC-A-600, IPC-A-610, or related PCB design and workmanship standards
  • Experience mentoring other PCB designers and improving layout libraries, workflows, checklists, or release processes
  • Experience with rigid-flex designs, thermal management, high-current power delivery, low-noise clocking, or low-jitter systems
Compensation Range : (For HR only)

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

The annual base salary range for this role is $124,920 – $171,770. The final offer is determined by factors such as location, experience, education, and training.


In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered:

401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime:

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Sr. Engineer, Infrastructure PBC Layout
Sr. Engineer, Infrastructure PBC Layout

SiTime Corp. • Santa Clara (CA)

On-site
USD 125,000 - 172,000
Sr. Engineer, Layout Design
Sr. Engineer, Layout Design

SiTime • Santa Clara (CA)

On-site
USD 125,000 - 172,000
Equity grants
401k plan
Health benefits
Principal Engineer, CAD
Principal Engineer, CAD

SiTime Corp. • Santa Clara (CA)

On-site
USD 148,000 - 204,000
401k plan
Health and wellness (medical/dental/ve
Principal Engineer, CAD
Principal Engineer, CAD

Sitime-Corporation • Tempe (AZ)

On-site
USD 161,000 - 230,000
401k plan
Health and wellness
Equity grants
+1
Principal Engineer, CAD
Principal Engineer, CAD

ADP, Inc. • Tempe (AZ)

On-site
USD 161,000 - 230,000
401k plan
Health and wellness program
Parental leave
+2
Principal Engineer, CAD
Principal Engineer, CAD

SiTime • Tempe (AZ)

On-site
USD 161,000 - 230,000
401k plan
Health and wellness benefits (medical,
Dental coverage
+5
Sr. Director, Package Development Engineering
Sr. Director, Package Development Engineering

Sitime-Corporation • Santa Clara (CA)

On-site
USD 239,000 - 342,000
Equity grants
401k plan
Health and wellness
Senior PCB Layout Engineer — High-Density, High-Speed
Senior PCB Layout Engineer — High-Density, High-Speed

ADP, Inc. • Santa Clara (CA)

On-site
USD 125,000 - 172,000
401k plan
Health and wellness benefits
Parental leave
+1
Sr. Staff Product Engineer
Sr. Staff Product Engineer

Sitime-Corporation • Tempe (AZ)

On-site
USD 135,000 - 165,000
401k plan
Health and wellness benefits
Parental leave
+1
Sr. Director, Package Development Engineering
Sr. Director, Package Development Engineering

SiTime Corp. • Santa Clara (CA), Northern (KY)

On-site
USD 239,000 - 342,000
401k plan
Health and wellness program
Parental leave