Principal Engineer, CAD

ADP, Inc.; Tempe (AZ); On-site; USD 161,000 - 230,000; Full time

Benefits offered by this job

401k plan

Health and wellness program

Parental leave

Legal services

Time off plans

Job summary

SiTime is seeking a Principal Engineer, CAD in Tempe, AZ to provide CAD software support for Digital, Analog and Mixed‑Signal designs using major EDA tools. The role includes tool development, installation, and deployment of new CAD tool flows across multiple sites.

The candidate will own PDK installation and release management, support end‑to‑end tapeouts, and interface with EDA vendors, delivering robust design tools and workflows. Strong Linux and scripting skills are required.

Qualifications

• BA/BS Degree in Electrical Engineering or Computer Science or related field.
• Minimum 7 years of experience with analog and digital new product development CMOS IC CAD support using EDA tools.
• Experience with Cadence Virtuoso Schematic Editor and Layout Suite, Spectre, Spectre‑RF, Multi‑Mode Simulator, Physical Layout tools, Assura, PVS, Pegasus, Innovus, Tempus.
• Experience with Siemens Analog Fast‑Spice, Questa, Parasitic CALIBRE PVS, XRC.
• Experience with Synopsys Design Compiler, VCS, SpyGlass and other tools.
• Programming languages: DFII SKILL, PERL, MATLAB, Tcl/Tk, C / C++, Python.
• Proficient at Linux OS, utilities, and scripting.
• Excellent written and verbal communication skills.
• Ability to work in a fast‑paced, collaborative environment.

Responsibilities

• Provide full lifecycle support for custom CAD flows across Cadence, Synopsys, Siemens and Keysight platforms.
• Own PDK installation, validation, customization, maintenance and release management.
• Support tapeout flows, coordinating tapeout submissions to foundries and ensuring schedule/quality adherence.
• Support Schematic Capture, Analog and Mixed‑signal Simulation, Layout and verification workflows.
• Maintain digital simulation and verification environments and digital P&R tools.
• Develop CAD utilities, automation scripts and regression flows to improve efficiency.
• Perform Functional Evaluation, Performance Benchmarking and deployment of new tools.
• Provide CAD Software & Linux User Support for CMOS Design Engineers & IC Layout Designers.
• Prepare and maintain user documentation, best practices and training materials.

Skills

Communication

Team collaboration

Problem solving

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Cadence Virtuoso

Spectre

Questa

Parasitic CALIBRE

Synopsys Design Compiler

VCS

SpyGlass

Innovus

Tempus

DFII SKILL

PERL

MATLAB

Tcl/Tk

C/C++

Python

Linux scripting

Job description

If you are unable to complete this application due to a disability, contact this employer to ask for an accommodation or an alternative application process.

Principal Engineer, CAD

Full-time Regular Professional Tempe, AZ, US

2 days ago Requisition ID: 1769

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com .

Job Summary

The Principal Engineer, CAD will provide CAD Software support for Digital, Analog and Mixed‑Signal designs, using Cadence, Synopsys, Siemens, Keysight & 3 rd party vendor tools. Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed‑Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support, implementation and testing of new software tools and deploy new CAD Tool flows. The Principal CAD Engineer will also interface with EDA Tool Vendors and have responsibilities for implementation and performance testing of new software releases, prior to deploying to IC Designers across multiple engineering sites.

Responsibilities:

• Provide full lifecycle support for custom CAD flows, including tool development, installation, configuration, maintenance and upgrades across Cadence, Synopsys, Siemens and Keysight platforms
• Own PDK installation, validation, customization, maintenance and release management, ensuring alignment with foundry and keeping up to date versions always ready
• Support and maintain end‑to‑end tapeout flows, including coordinating and executing tapeout submissions to foundries, ensuring compliance with foundry requirements, schedules and quality standards
• Support Schematic Capture, Analog and Mixed‑signal Simulation, Layout and Layout Verification software and workflows using established revision‑controlled processes
• Support and maintain digital simulation, verification environments, digital place‑and‑route tools
• Develop and maintain CAD utilities, automation scripts and regression flows to improve design efficiency and consistency
• Perform Functional Evaluation, Performance Benchmarking and Deployment of New Tools
• Provide CAD Software & Linux User Support for CMOS Design Engineers & IC Layout Designers
• Prepare and maintain clear user documentation, best practices and training material for design teams across sites
• Responsible for diagnosis, resolution, regression of reported problems in a timely manner
• Interfacing directly with EDA Vendors’ Application and support teams to resolve and influence product improvements
• Support additional CAD‑related initiatives and projects as assigned

Qualifications & Requirements:

• BA/BS Degree in Electrical Engineering, Computer Science or related field
• Minimum 7 years of experience with analog and digital new product development CMOS IC CAD support using EDA tools
• Must have experience supporting:
  • 1. Cadence Virtuoso Schematic Editor and Layout Suite, Spectre, Spectre‑RF, Multi‑Mode Simulator, Physical Layout tools, Assura, PVS, Pegasus, Innovus, Tempus
  • 2. Siemens Analog Fast‑Spice, Questa, Parasitic CALIBRE PVS, XRC
  • 3. Synopsys Design Compiler, VCS, SpyGlass and other tools
  • Programming languages: DFII SKILL, PERL, MATLAB, Tcl/Tk, C / C++, Python
  • Proficient at Linux OS, utilities, and scripting

Desired Characteristics & Attributes:

• Excellent written and verbal communication skills required
• Ability to work well with others in a fast‑paced collaborative team environment
• Strong problem‑solving skills, attention to detail and a proactive approach to continuous improvement.

Compensation Range:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

T he annual base salary range for this role is $160,920.00 – $230,140.00 . The final offer is determined by factors such as location, experience, education, and training.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E‑Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.