ASIC Design Verification Engineer, Amazon Leo

WarmStart Ltd; Redmond, Northern (WA, KY); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in Redmond, WA seeks an ASIC Design Verification Engineer to advance digital SOC verification for satellite communication. You will implement VERILOG-based verification, build regression environments, and collaborate across design teams on system-level verification using UVM, SystemC, and DPI-C.

The role requires a strong background in electrical engineering, 5+ years of verification experience, and 2+ years with UVM, C, and scripting.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of verification experience, preferably in communication systems.
• 2+ years of experience with UVM, C, and scripting.

Responsibilities

• Implement a state-of-the-art verification environment for RTL versus reference Matlab/C models.
• Develop test plans, write tests, run regressions, and report progress to the program.
• Validate ASIC implementations in Verilog/SystemVerilog.
• Conduct formal verification of complex blocks to ensure functional correctness.
• Collaborate with design and systems teams for system-level verification using UVM, SystemC, and DPI-C.
• Create a highly automated regression environment and maintain database organization.

Skills

UVM

C

Scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering (preferred)

Tools

Verilog/SystemVerilog

SystemC

DPI-C

Matlab

Job description

ASIC Design Verification Engineer, Amazon Leo

Amazon Kuiper Manufacturing Enterprises LLC, Redmond, WA

Job Description:

Amazon Leo is seeking a skilled engineer to join its team focused on developing digital chip SOCs for communication via Low Earth Orbit satellites. This role offers the chance to create innovative wireless solutions that enhance connectivity for various customers, including households, schools, and businesses.

Responsibilities:

• Implement a state-of-the-art verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Conduct formal verification of complex blocks to ensure functional correctness.
• Collaborate with design and communication systems teams for system-level verification using UVM, SystemC, and DPI-C.
• Create a highly automated environment for running regressions and maintaining database organization.

Qualifications:

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in verification, preferably in communication systems.
• 2+ years of experience with UVM, C, and scripting.

Skills:

• Master's degree in Electrical or Communications Engineering (preferred).
• 7+ years of digital verification experience in communication systems (preferred).
• Familiarity with Matlab and modem design verification.
• Experience in System C or Matlab model development or DV integration.
• Knowledge of formal verification techniques.
• Strong written and verbal communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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