Sr Architect, Technical Product Manager (3DIC Packaging)

Synopsys, Inc.; Northern (KY); Hybrid; USD 180,000 - 270,000; Full time

Job summary

Synopsys, Inc. is seeking a senior technical product leader with deep IC packaging experience to guide multi-die packaging roadmaps and signoff analysis.

You will collaborate with customers, foundries, and OSATs to translate packaging challenges into prioritized requirements and drive AI-driven workflows across silicon, advanced package, and substrate flows. You will work with engineering teams to define capabilities, evaluate tradeoffs, and validate solutions, while presenting the technical

Qualifications

• 15+ years in semiconductor IC packaging, design, analysis and production tapeout.
• Hands-on expertise with industry-standard silicon and package design tools.
• Experience with SI/PI, thermal and mechanical analyses for advanced packages.
• Familiarity with 2.5D/3DIC, chiplet, HBM, photonics and co-packaged optics.
• Knowledge of PCIe, DDR, and HBM interfaces in packaging context.
• Ability to translate complex challenges into clear requirements and roadmap priorities.
• Experience collaborating with foundries, OSATs and ecosystem partners.

Responsibilities

• Develop the technical roadmap for multi-die advanced package design, implementation, and signoff analysis.
• Engage with customers, foundries, and OSATs to translate packaging challenges into prioritized requirements.
• Evaluate the competitive landscape and emerging technologies to guide roadmap priorities.
• Work hands-on with engineering teams to define capabilities and validate solutions across flows.
• Drive cross-functional delivery addressing package implementation, SI/PI, multiphysics, and manufacturing challenges.
• Advance AI-driven workflows for multi-die design, multiphysics analysis, and optimization.
• Present the technical vision and roadmap to executives, customers, and ecosystem partners.
• Provide technical direction to field teams supporting evaluations and deployments.

Skills

IC packaging design

Package analysis

Production tapeout flows

Multi-die architectures

2.5D/3DIC

Chiplet

HBM

AI-driven workflows

Roadmap development

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with customers across industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a senior technical product leader with hands-on experience in IC packaging design, package analysis, and production tapeout flows. You have worked directly with multi-die and package layout tools, and SI/PI, thermal and mechanical analysis flows.

You understand 2.5/3DIC, chiplet, HBM, photonics, and co-packaged optics architectures and can engage credibly with architects, silicon and package engineering teams, foundries, OSATs, and ecosystem partners.

This Technical Product Management role requires substantial engineering depth. Success depends on understanding the technology, design flows, and implementation challenges well enough to guide roadmap priorities, define detailed requirements, and validate solutions against real packaging problems.

What You’ll Be Doing

• Develop the technical roadmap for multi-die advanced package design, implementation, and signoff analysis.
• Engage with customers, foundries, and OSATs to translatepackaging challenges into prioritizedrequirements.
• Evaluate the competitive landscape, emerging technologies, and evolving design methodologies to guide roadmap priorities and position Synopsys offerings with technical clarity.
• Work hands‑on with engineering teams to define capabilities, evaluate technical tradeoffs, andvalidatesolutions across silicon, advanced package, and package substrate flows.
• Drive cross-functional delivery of solutions addressing package implementation, SI/PI, multiphysics, and manufacturing challenges.
• Advance AI-driven and agentic workflows for multi-die design, multiphysics analysis, and optimization.
• Present the technical product vision and roadmap to executives, customers, and ecosystem partners, and represent Synopsys at industry events and standards engagements.
• Provide technical direction tofield teams supporting customer evaluations and deployments.

The Impact You Will Have

• Enable next-generation AI accelerators, high-performance computing, and data-center silicon built on advanced multi-die architectures.
• Expand Synopsys’multi-diepackaging presence through differentiated package design, multiphysics, analysis, and production solutions.

• Drive adoption across semiconductor companies, hyperscalers, and design service providers by aligning product capabilities with production tapeout requirements.
• Strengthen foundryand OSATpartnerships through technical roadmap alignment and co-development.
• Enable customers to scale multi-die advanced packages by addressing complex implementation, SI/PI, thermal, mechanical, and system integration challenges.

What You’ll Need

• 15+ years of semiconductor IC and packaging experience.
• Deep technical knowledge of IC and packagedesign, analysis, manufacturing, and production tapeout.
• Hands-onexpertisewith industry-standardsilicon and packagedesign tools, SI/PI analysis tools, and related production flows.
• Expertisein signal integrity, power integrity, EMIR, thermal, and mechanical analysis for advanced packages.
• Experience with2.5D/3DIC,chiplet, HBM, photonics, and co-packaged optics architectures&methodologies.
• Familiarity with high-speed interfaces such as PCIe, DDR, and HBM in the context of packagedesign & signoff.
• Understanding of AI-driven and agentic workflows for design automation,analysis, and optimization.
• Experience working with semiconductor companies, hyperscalers, foundries, OSATs, and ecosystem partners.
• Demonstrated ability to translate complex technical challenges intorequirements and roadmap priorities.