SPE Signal Integrity Engineer

USA Tech Recruit; Atlanta (GA); On-site; USD 120,000 - 180,000; Full time

Job summary

USA Tech Recruit, partnering with a Johns Creek, GA based tech leader, seeks an experienced SPE Signal Integrity Engineer to advance high-speed memory subsystems and security solutions.

You will report to the VP of Engineering and contribute to modelling, analysis, and simulations up to 12800+ MT/s DDR4/5. The role emphasizes SI/PI, package/PCB design, and lab validation with strong cross-functional collaboration.

Qualifications

• MS or PhD in Electrical Engineering with 10+ years of industry experience, DDR4/5 exposure.
• Solid background in SI/PI and package design to provide technical leadership.
• Strong interpersonal skills to lead and motivate the team.
• Experience simulating high-speed memory (DDR4/5) and SERDES interfaces.
• Strong understanding of EM, transmission line theory, and equalization techniques (FIR/FFE/DFE/CTLE).
• Familiarity with editing APD/Allegro layout files and SI/PI-driven BGA trade-offs.
• Experience correlating simulations with lab measurements (scopes, TDRs, VNAs).
• Excellent writing and presentation skills; ability to work cross-functionally.

Responsibilities

• Create SI/PI methodologies and work with Design and SI teams for SI/PI study and package design for DDR products.
• Define specifications and system design requirements including packaging, PCB routings, and decoupling.
• Provide guidelines to design teams based on SI/PI studies and silicon correlation for best SI performance.
• Collaborate with customers to find optimum SI/PI solutions.
• Assist the team with debugging and lab bring-up as needed.

Skills

SI/PI analysis

DDR4/DDR5 knowledge

Spice/ADS simulations

EM theory

Package/PCB design

Lab measurements correlation

Customer collaboration

Education

MS or PhD in Electrical Engineering

Tools

ADS

HFSS

Q3D/PowerSI

Virtuoso

RedHawk/Totem

VNA/TDR

Job description

USA Tech Recruit are working closely with a leading technology company specializing in high-performance memory subsystems, interface IP and security solutions, based in Johns Creek, who are looking for an experienced SPE Signal Integrity Engineer to join their team.

As an SPE Signal Integrity Engineer, you will be reporting directly to the VP of Engineering. You will work within their SI/PI team to work on modelling, analysis, and simulations of signal integrity and power integrity in the very challenging DDR field with speed up to 12800+ MT/s.

Responsibilities as SPE Signal Integrity Engineer:

• Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio.
• Work with the design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis.
• Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that products will have superior SI performance, i.e. best RMT scores.
• Work with customers to do collaboration to find the optimum SI/PI solution.
• Help the team during debug and bring up in lab if needed.

Requirements:

• MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5.
• Solid background in SI/PI and package design to provide technical leadership to the team.
• Strong interpersonal skill to keep the team motivated and focused.
• Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required.
• Solid theoretical background and understanding in EM and transmission line theory is a must.
• Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required.
• Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system.
• Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc.
• Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable.
• Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations.
• Proficient with simulations using Spice and ADS.
• Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI.
• Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus.
• Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus.
• Basic knowledge of circuits used in high-speed link design is preferred.
• Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams.
• Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player.

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