Space Systems FPGA & VLSI Engineer

Medium; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Health benefits

Paid time off

Professional development

Competitive salary

Job summary

E-Space, based in Saratoga, California, is hiring a design-focused RTL/FPGA engineer to join our space-tech team. You will design and implement SystemVerilog RTL, validate FPGA platforms, and collaborate across verification, ASIC, and software teams to ensure timing-safe, high-performance hardware for a LEO satellite system.

The role is full-time, exempt, with competitive compensation and opportunities to impact next-gen space communications.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Strong experience writing synthesizable SystemVerilog/Verilog.
• Proven experience with FPGA development flows, including synthesis, implementation, and validation.
• Solid understanding of digital design fundamentals and timing analysis.

Responsibilities

• Design and implement RTL using SystemVerilog with consideration for timing, power, and area.
• Perform FPGA prototyping, validation, and hardware bring-up for digital designs.
• Develop and execute simulation and debugging strategies at block and subsystem levels.
• Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals.
• Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns.
• Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance.
• Participate in design reviews and contribute to improving design quality and best practices.

Skills

SystemVerilog

FPGA development

Digital design

Timing analysis

Education

Electrical/Computer Engineering (BS/MS/PhD)

Tools

Xilinx/Intel FPGA toolchains

Xilinx Vivado/Intel Quartus

Job description

E-Space, based in Saratoga, California, is hiring a design-focused RTL/FPGA engineer to join our space-tech team. You will design and implement SystemVerilog RTL, validate FPGA platforms, and collaborate across verification, ASIC, and software teams to ensure timing-safe, high-performance hardware for a LEO satellite system.

The role is full-time, exempt, with competitive compensation and opportunities to impact next-gen space communications.