Space-Grade ASIC Physical Design Engineer

Anysilicon; Northern, Los Angeles (KY, CA); Hybrid; USD 100,000 - 140,000; Full time

Job summary

K2 is seeking an ASIC Physical Design Engineer to design advanced SoCs for satellite systems. You will lead the full physical design flow, from synthesis to tapeout, and collaborate with DFT and sign-off teams in a fast-paced space tech environment.

Required: 2+ years in ASIC physical design, strong tool experience (ICC2/Fusion Compiler, Innovus), and knowledge of timing, power, and verification flows. FinFET and space-grade design familiarity is a plus.

Qualifications

• 2+ years of ASIC physical design experience for complex SoCs.
• Hands-on with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus).
• Familiar with FinFET, DFT/UPF/CPF, ECO implementation.

Responsibilities

• Execute full physical design flow for complex SoC blocks and top-level.
• Perform timing closure across corners and modes.
• Collaborate with DFT teams to ensure timing convergence.
• Develop scripts to automate flow and improve efficiency.
• Support sign-off activities: DRC/LVS, STA, EM, SI, power analysis.
• Assist chip-level integration and tapeout prep.
• Contribute to methodology development and tool evaluation.

Skills

ASIC physical design

Timing optimization

DFT knowledge

Scripting/automation

Problem-solving

Education

Bachelor's in Electrical/Computer Engineering

Master's degree preferred

Tools

Synopsys ICC2/Fusion Compiler

Cadence Innovus

Timing analysis tools

Job description

K2 is seeking an ASIC Physical Design Engineer to design advanced SoCs for satellite systems. You will lead the full physical design flow, from synthesis to tapeout, and collaborate with DFT and sign-off teams in a fast-paced space tech environment.

Required: 2+ years in ASIC physical design, strong tool experience (ICC2/Fusion Compiler, Innovus), and knowledge of timing, power, and verification flows. FinFET and space-grade design familiarity is a plus.