ASIC Physical Design Engineer

Anysilicon; Northern, Los Angeles (KY, CA); Hybrid; USD 100,000 - 140,000; Full time

Job summary

K2 is seeking an ASIC Physical Design Engineer to design advanced SoCs for satellite systems. You will lead the full physical design flow, from synthesis to tapeout, and collaborate with DFT and sign-off teams in a fast-paced space tech environment.

Required: 2+ years in ASIC physical design, strong tool experience (ICC2/Fusion Compiler, Innovus), and knowledge of timing, power, and verification flows. FinFET and space-grade design familiarity is a plus.

Qualifications

• 2+ years of ASIC physical design experience for complex SoCs.
• Hands-on with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus).
• Familiar with FinFET, DFT/UPF/CPF, ECO implementation.

Responsibilities

• Execute full physical design flow for complex SoC blocks and top-level.
• Perform timing closure across corners and modes.
• Collaborate with DFT teams to ensure timing convergence.
• Develop scripts to automate flow and improve efficiency.
• Support sign-off activities: DRC/LVS, STA, EM, SI, power analysis.
• Assist chip-level integration and tapeout prep.
• Contribute to methodology development and tool evaluation.

Skills

ASIC physical design

Timing optimization

DFT knowledge

Scripting/automation

Problem-solving

Education

Bachelor's in Electrical/Computer Engineering

Master's degree preferred

Tools

Synopsys ICC2/Fusion Compiler

Cadence Innovus

Timing analysis tools

Job description

K2 is a pioneering space startup focused on developing the largest and highest-power satellites ever flown, backed by significant investment and contracts. The company aims to revolutionize satellite technology for missions ranging from Low Earth Orbit (LEO) to deep space, leveraging advancements in heavy-lift launch vehicles. K2 is seeking an ASIC Physical Design Engineer to contribute to the design of advanced System on Chips (SoCs) for next-generation satellite systems.

Responsibilities:

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
• Collaborate with DFT teams to ensure clean timing convergence.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign-off activities including DRC/LVS, STA, EM, Signal Integrity, and power analysis.
• Assist in chip-level integration, timing and functional ECOs, and tapeout preparation.
• Contribute to methodology development, tool evaluation, and flow documentation.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 2+ years of experience in ASIC physical design for complex SoCs.
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
• Strong understanding of timing analysis, power optimization, and physical verification flows.
• Experience with hierarchical or flat SoC design methodologies.
• Familiarity with FinFET technologies.
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Skills:

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience with sign-off through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

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• Verification
• Packaging & Wafer
• Semiconductor IP

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