Senior ASIC Physical Design Engineer

K2 Space; United States; Remote; USD 170,000 - 250,000; Full time

Benefits offered by this job

Equity in the company

Comprehensive benefits package

Paid time off

Medical/dental/vision coverage

Life insurance

Job summary

A pioneering space technology company is seeking a Senior ASIC Physical Design Engineer to implement advanced SoCs for next-generation satellite systems. This role involves collaboration with architecture, RTL, and verification teams, contributing to all phases of the physical design flow, including timing closure and optimization. Candidates should have 5-10 years of experience in ASIC physical design along with relevant educational qualifications. Competitive compensation starts at $170,000, plus equity and comprehensive benefits.

Qualifications

• 5–10 years of experience in ASIC physical design for complex SoCs.
• Hands-on experience with industry-standard tools for physical design.
• Strong understanding of timing analysis and physical verification.

Responsibilities

• Execute complete physical design flow for complex SoC blocks.
• Perform timing closure and optimization using industry-standard tools.
• Develop and maintain scripts to improve flow efficiency.

Skills

Timing analysis

Power optimization

Physical verification

Problem-solving skills

Collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Synopsys ICC2/Fusion Compiler

Cadence Innovus

Job description

Overview

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels across every orbit. Backed by $450M from leading investors and with an additional $500M in signed contracts across commercial and US government customers, we’re mass-producing the highest-power satellite platforms for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry to mass abundance. Engineered to survive harsh radiation environments and to capitalize on today’s and tomorrow’s rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. We are building bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are driven and excited about contributing to a groundbreaking Series C space startup, we’d love for you to apply.

The Role

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. You will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful satellites deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will contribute to developing cutting-edge SoCs that will fly in space.

Responsibilities

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
• Assist in chip-level integration, ECOs, and tapeout preparation.
• Contribute to methodology development, tool evaluation, and flow documentation.
• Support your product through production and spaceflight.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5–10 years of experience in ASIC physical design for complex SoCs.
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
• Strong understanding of timing analysis, power optimization, and physical verification flows.
• Experience with hierarchical or flat SoC design methodologies.
• Familiarity with FinFET technologies.
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience with sign-off through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on factors including knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and other perks

Export Compliance: The person hired for this role will have access to information and items controlled by U.S. export control regulations, including ITAR. The role requires compliance with U.S. export control laws and ITAR regulations.

K2 Space is an Equal Opportunity Employer and will not be influenced in hiring by race, color, religion, gender, national origin, veteran status, disability status, age, sexual orientation, gender identity, or other legally protected status.