Software Engineer II - High-Performance Chip Design Tools

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 102,000 - 189,000; Full time

Job summary

Cadence Design Systems is seeking a Software Engineer II for the Innovus R&D team in San Jose, CA. You will contribute to next-generation physical design tech, implementing algorithms for placement, routing, and optimization on scalable Linux systems.

You will collaborate with diverse teams and advance Innovus through performance tuning, debugging, and feature improvements, working on high-impact semiconductor design flows. This role targets a strong foundation in CS/EE and C/C++ expertise.

Qualifications

• MS in Computer Science, Electrical Engineering, or related field.
• Strong foundation in algorithms, data structures, and problem-solving.
• Proficiency in C/C++ and software development on UNIX/Linux systems.
• Strong analytical and debugging skills.
• Ability to work effectively in a collaborative, team-oriented environment.

Responsibilities

• Design, implement, and optimize algorithms for physical synthesis, placement, and routing engines.
• Develop high-performance, scalable software using C/C++ on Linux/UNIX platforms.
• Contribute to the Innovus digital implementation flow, including timing, power, and optimization.
• Collaborate with cross-functional teams to define requirements and deliver high-quality solutions.
• Analyze performance bottlenecks and improve runtime, scalability, and quality of results (PPA).
• Debug, troubleshoot, and enhance existing features within the Innovus platform.

Skills

C/C++

UNIX/Linux

Algorithms

Problem solving

Education

MS in Computer Science/ Electrical Engineering

Job description

Cadence Design Systems is seeking a Software Engineer II for the Innovus R&D team in San Jose, CA. You will contribute to next-generation physical design tech, implementing algorithms for placement, routing, and optimization on scalable Linux systems.

You will collaborate with diverse teams and advance Innovus through performance tuning, debugging, and feature improvements, working on high-impact semiconductor design flows. This role targets a strong foundation in CS/EE and C/C++ expertise.