SoC Verification Engineer: High-Impact ASIC DSP

Socket.dev; South San Francisco (CA); On-site; USD 131,000 - 243,000; Full time

Benefits offered by this job

Excellent medical, dental, and vision

Paid holidays

Commuter benefits

Meals provided

RSUs for full-time employees

401(k) plan

Job summary

Neuralink is seeking ASIC Design Verification Engineers to join the SoC Implant Team. You will work on high-throughput, low-power DSP verification for brain-computer interface tech. The role emphasizes SystemVerilog proficiency, test bench development, and automation scripting in a collaborative environment.

We offer equity (RSUs) and a comprehensive benefits package for full-time staff, with a base salary range of $131,000 to $243,000 depending on experience and education.

Qualifications

• Minimum 3 years of digital ASIC verification experience.
• Excellence in SystemVerilog.
• Experience developing automation flows using Python, Perl, Makefile, Tcl, and UNIX shell.
• Experience with code coverage and regression setup.

Responsibilities

• Verify digital ASIC designs within the SoC team.
• Build and maintain test benches and verification environments.
• Debug complex digital systems and collaborate on architecture decisions.

Skills

SystemVerilog

Automation scripts

Code coverage & regression

Tools

UVM

UPF flow

FPGA/Emulation

Job description

Neuralink is seeking ASIC Design Verification Engineers to join the SoC Implant Team. You will work on high-throughput, low-power DSP verification for brain-computer interface tech. The role emphasizes SystemVerilog proficiency, test bench development, and automation scripting in a collaborative environment.

We offer equity (RSUs) and a comprehensive benefits package for full-time staff, with a base salary range of $131,000 to $243,000 depending on experience and education.