SoC Validation Engineer - Power Management

Intel Corporation; Folsom (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Intel Corporation in California seeks a SoC Validation Engineer to join the Power Management Validation team. You will validate power management architectures and DVFS, power gating, clock gating, reset flows, and low-power states across complex SoC designs.

Collaborate with architecture, design, and verification teams, develop validation environments using SystemVerilog/UVM, and drive debug to improve product quality and readiness.

Qualifications

• Bachelor's degree or higher in Electrical/Computer Engineering, Computer Engineering, or related technical field.
• Experience in pre-silicon validation, functional validation, design verification, or silicon validation.
• Strong understanding of digital design fundamentals and SoC design concepts.
• Experience with SystemVerilog/UVM-based validation methodologies.
• Proficiency with Python/Shell/Perl for automation.

Responsibilities

• Develop and execute validation plans for power management features across SoCs.
• Create and maintain validation environments, test content, and debug infrastructure.
• Validate DVFS, power gating, clock gating, reset flows, and low-power states.
• Develop validation content and infrastructure using SystemVerilog, UVM, and associated tools.
• Analyze validation results and drive root-cause analysis with cross-functional teams.

Skills

Digital design fundamentals

SoC design concepts

Debugging and root-cause analysis

Pre-silicon validation

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in Electrical/Computer Engineering

PhD in a related technical field

Tools

SystemVerilog

UVM

Simulation/Emulation platforms

Python

Job description

Job Details:

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Role and Impact:

Intel is seeking a motivated and experienced SoC Validation Engineer to join our Power Management Validation team. In this role, you will be responsible for validating power management architectures and features that enable Intel's next-generation products. You will play a critical role in ensuring design quality, functionality, and power efficiency by developing innovative validation strategies, executing comprehensive test plans, and driving debug activities across complex SoC designs.

As a SoC Power Management Validation Engineer, you will work closely with architecture, design, and verification teams to validate key power management features including Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, reset flows, low-power states, thermal management, and telemetry. You will contribute to the development of advanced validation environments, uncover design issues early in the development cycle, and drive solutions that improve product quality and readiness. This position offers an opportunity to influence future Intel products while expanding your technical leadership and validation expertise.

Business group:

You will be joining Intel's Data Center Group (DCG), a global leader in designing and delivering cutting-edge technologies that drive data center innovation and transformation. The group specializes in developing high-performance solutions to accelerate computing, storage, and networking capabilities, supporting Intel's mission to power the world's digital infrastructure.

Key Responsibilities:

• Develop and execute comprehensive validation plans to ensure power management features meet architectural and functional specifications.
• Design, develop, and maintain validation environments, automated test content, and debug infrastructure for power management validation.
• Validate critical power management features including: Dynamic Voltage and Frequency Scaling (DVFS), Power Gating and Clock Gating, Low-Power States and Power State Transitions, Reset and Power Sequencing, Thermal Management Features, Telemetry and Monitoring Logic.
• Develop validation content and infrastructure using industry-standard methodologies and tools such as SystemVerilog, UVM, simulation, and emulation platforms.
• Execute simulation and emulation workloads to validate design functionality and identify issues early in the product development cycle.
• Analyze validation results, coverage metrics, and performance data to improve design quality and validation effectiveness.
• Drive root cause analysis, debug, and resolution of complex design issues in collaboration with architecture, RTL design, and verification teams.
• Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools to improve validation efficiency and coverage.
• Review architecture specifications and design changes to assess validation impact and ensure comprehensive feature coverage.
• Contribute to validation methodology improvements and best practices across multiple product generations.
• Mentor junior engineers and provide technical leadership on complex validation and debug challenges.
• Continuously explore new technologies, automation techniques, and AI-assisted solutions to improve execution and outcomes.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

• Bachelors & 6+ years or Masters & 4+ years or PhD & 2+ years degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
• Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
• Strong knowledge of SystemVerilog and UVM-based validation methodologies.
• Experience with simulation or emulation environments, debugging and root-cause analysis skills.
• Knowledge in Python or Perl or Shell, or simi