Senior SoC Power Management Validation Engineer

Intel Corporation; Folsom (CA); On-site; USD 164,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Job summary

Intel Corporation in California, USA is seeking a highly experienced SoC Power Management Validation Engineer within the Data Center Group. You will validate dynamic voltage/frequency scaling, power gating, clock gating, reset flows, and telemetry across complex SoCs, partnering with architecture, design, and verification teams to ensure high-quality, power-efficient silicon products.

The role emphasizes developing advanced validation environments, automated test content, and debugging

Qualifications

• Bachelors 6+ years or Masters 4+ years or PhD 2+ years in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
• Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
• Strong knowledge of SystemVerilog and UVM-based validation methodologies.
• Experience with simulation or emulation environments, debugging and root-cause analysis skills.
• Knowledge in Python or Perl or Shell, or similar scripting languages.

Responsibilities

• Develop and execute comprehensive validation plans for power management features.
• Design, develop, and maintain validation environments, automated test content, and debug infrastructure.
• Validate features including DVFS, Power/Clock Gating, Low-Power States, and Telemetry.
• Develop validation content using SystemVerilog, UVM, simulation, and emulation platforms.
• Execute simulation and emulation workloads to validate design functionality and identify issues.
• Analyze results, coverage metrics, and performance data to improve validation.
• Lead root cause analysis and collaborate with architecture, RTL, and verification teams.
• Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools.
• Review architecture specs and design changes to assess validation impact.
• Contribute to validation methodology improvements and mentor junior engineers.
• Explore new technologies and AI-assisted solutions to improve execution.

Skills

SystemVerilog & UVM

Python

Debugging & root-cause

SoC design concepts

Digital design fundamentals

Education

Bachelor's in ECE/CE/CS

Master's degree

PhD

Tools

Simulation & Emulation

Job description

Intel Corporation in California, USA is seeking a highly experienced SoC Power Management Validation Engineer within the Data Center Group. You will validate dynamic voltage/frequency scaling, power gating, clock gating, reset flows, and telemetry across complex SoCs, partnering with architecture, design, and verification teams to ensure high-quality, power-efficient silicon products.

The role emphasizes developing advanced validation environments, automated test content, and debugging