Senior SoC Power Management Validation Engineer

Intel Corporation; Folsom (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Intel Corporation in California seeks a SoC Validation Engineer to join the Power Management Validation team. You will validate power management architectures and DVFS, power gating, clock gating, reset flows, and low-power states across complex SoC designs.

Collaborate with architecture, design, and verification teams, develop validation environments using SystemVerilog/UVM, and drive debug to improve product quality and readiness.

Qualifications

• Bachelor's degree or higher in Electrical/Computer Engineering, Computer Engineering, or related technical field.
• Experience in pre-silicon validation, functional validation, design verification, or silicon validation.
• Strong understanding of digital design fundamentals and SoC design concepts.
• Experience with SystemVerilog/UVM-based validation methodologies.
• Proficiency with Python/Shell/Perl for automation.

Responsibilities

• Develop and execute validation plans for power management features across SoCs.
• Create and maintain validation environments, test content, and debug infrastructure.
• Validate DVFS, power gating, clock gating, reset flows, and low-power states.
• Develop validation content and infrastructure using SystemVerilog, UVM, and associated tools.
• Analyze validation results and drive root-cause analysis with cross-functional teams.

Skills

Digital design fundamentals

SoC design concepts

Debugging and root-cause analysis

Pre-silicon validation

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in Electrical/Computer Engineering

PhD in a related technical field

Tools

SystemVerilog

UVM

Simulation/Emulation platforms

Python

Job description

Intel Corporation in California seeks a SoC Validation Engineer to join the Power Management Validation team. You will validate power management architectures and DVFS, power gating, clock gating, reset flows, and low-power states across complex SoC designs.

Collaborate with architecture, design, and verification teams, develop validation environments using SystemVerilog/UVM, and drive debug to improve product quality and readiness.