SoC UPF Methodology Engineer

Apple, Inc.; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Apple, Inc. invites a Power UPF Engineer to advance the Unified Power Format for next‑gen mobile SOCs. You will enhance UPF methodologies, specify power intent, and verify implementations across frontend and place‑and‑route stages.

Collaboration with design and verification teams is essential to resolve UPF workflow challenges. Ideal candidates bring UPF implementation and verification experience, Python and Tcl scripting skills, and familiarity with multi‑voltage verification tools.

Qualifications

• A minimum of a bachelor's degree in a relevant field and at least 3 years of related industry experience.

Responsibilities

• Enhancing power intent coverage via static and dynamic verification techniques.
• Developing UPF solutions to align with project requirements.
• Overseeing UPF deployment and sign‑off for FE and P&R stages.
• Conducting thorough power intent assessments on custom circuitry.
• Partnering with design and verification teams to troubleshoot UPF workflows.
• Integrating AI/ML technologies to optimize UPF processes.

Skills

UPF expertise

Python scripting

Tcl scripting

AI/ML in design

Team collaboration

Education

Bachelor's degree in a relevant field

Tools

VSILP/VCLP

CLP

Job description

Are you passionate about crafting solutions to intricate challenges? Join the Low Power groupat Silicon Technologies and contribute to the development of cutting‑edge technology and capabilities for low‑power chip design. Your work will fuel Apple’s next‑generation chips!You’ll play a crucial role in exploring AI/ML to design the workflow for the next generation ofUPF. Additionally, you’ll refine our existing UPF framework and ensure its seamless integrationand rigorous verification across our mobile products.You will be part of an exciting silicon design group that is responsible for designing state‑of‑the‑art ASICs.We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign‑off and power intent-UPF implementation & verification on mobile SOCs.

Description

In this role, your main objective will be to enhance our Unified Power Format (UPF) methodologies, refining power intent specification, execution, and validation to support state‑of‑the‑art mobile SOCs.

Key responsibilities encompass:

• Enhancing power intent coverage via advanced static and dynamic verification techniques.
• Developing tailored UPF solutions to align with unique project requirements.
• Overseeing UPF deployment and sign‑off for frontend (FE) and place‑and‑route (P&R) stages.
• Conducting thorough power intent assessments on custom circuitry.
• Partnering with design and verification teams to troubleshoot and fix UPF‑related workflow challenges.
• Integrating AI/ML technologies to optimize UPF processes and methodologies.

Minimum Qualifications

• A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience

Preferred Qualifications

• Expertise in UPF implementation and verification.
• Proficiency in scripting with languages like Python and Tcl.
• Understanding of CMOS power design principles.
• Experience applying AI/ML to coding and workflow optimization.
• Knowledge of multi‑voltage static verification tools (e.g., VSILP/VCLP, CLP).
• Familiarity with the complete RTL‑to‑GDSII design flow.
• Strong communication abilities for effective collaboration across multidisciplinary teams.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.