SoC UPF Methodology Engineer — AI-Driven Power

Apple, Inc.; San Diego (CA); On-site; USD 142,000 - 263,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Discounted products and services

Educational reimbursement

Relocation assistance

Stock program eligibility

Job summary

Apple, Inc. is seeking a Power UPF Engineer in our Silicon Technologies Low Power group in California to advance UPF methodologies for next-generation mobile SOCs. You will influence power intent specification, verification, and integration across frontend and place-and-route stages.

You will apply AI/ML to optimize UPF processes, collaborate with cross-functional teams, and help drive transistor-level power ERC sign-off on state‑of‑the‑art chips for mobile devices.

Qualifications

• Bachelor's degree and at least 3 years of related industry experience.
• Expertise in UPF implementation and verification.
• Proficiency with Python and Tcl scripting.
• Understanding CMOS power design principles.
• Experience applying AI/ML to workflow optimization.
• Familiarity with RTL-to-GDSII design flow.
• Strong communication for cross-disciplinary collaboration.

Responsibilities

• Enhance UPF coverage with static and dynamic verification techniques.
• Develop UPF solutions tailored to project requirements.
• Oversee UPF deployment and sign-off for FE and P&R stages.
• Assess power intent on custom circuitry.
• Collaborate with design and verification teams to troubleshoot UPF workflows.
• Integrate AI/ML to optimize UPF processes.

Skills

UPF implementation

UPF verification

Python

Tcl

CMOS power design

AI/ML in flows

RTL-to-GDSII knowledge

Cross-functional collaboration

Education

Bachelor's degree in a relevant field

Tools

VSILP/VCLP/CLP

Job description

Apple, Inc. is seeking a Power UPF Engineer in our Silicon Technologies Low Power group in California to advance UPF methodologies for next-generation mobile SOCs. You will influence power intent specification, verification, and integration across frontend and place-and-route stages.

You will apply AI/ML to optimize UPF processes, collaborate with cross-functional teams, and help drive transistor-level power ERC sign-off on state‑of‑the‑art chips for mobile devices.