SoC Power & Thermal Validation Engineer

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a SoC Power Validation Engineer in San Diego, CA. You will validate CPU/GPU/DDR/NOC power at core and system level, performing Pre-Si and Post-Si validation across multiple IPs and refining power reduction techniques.

The role requires strong fundamentals in digital design, SoC power trees, and experience with automated data collection and analysis. Collaboration with architects and verification teams is essential in this dynamic environment.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field.
• Experience in ASIC design, verification, validation, or related work.
• Familiarity with Python or scripting for automation; debugging hardware/software issues.

Responsibilities

• Perform Pre-Si and Post-Si Power, thermal & performance correlation, debug, and analysis at the system level across various SoC IPs.
• Execute regression and PVT testing across different parts, lots, and wafers; analyze data and extract metrics.
• Collaborate with architects, designers, and verification engineers to define and execute validation plans and identify risk areas.
• Document observations and analysis; propose solutions to optimize hardware/software for low power consumption.
• Debug low-level software and hardware issues using tools like JTAG and kernel debuggers.
• Conduct Vmin/Fmax measurements and collect data for performance characterization.
• Automate validation flows and data collection using Python or similar languages.

Skills

Python scripting

JTAG debugging

Kernel debugging

C/C++ programming

Education

Bachelor’s degree in CS or EE

Master’s degree in CS or EE

Tools

Lauterbach TRACE32

Oscilloscope

Logic analyzers

Job description

Qualcomm Technologies, Inc. is seeking a SoC Power Validation Engineer in San Diego, CA. You will validate CPU/GPU/DDR/NOC power at core and system level, performing Pre-Si and Post-Si validation across multiple IPs and refining power reduction techniques.

The role requires strong fundamentals in digital design, SoC power trees, and experience with automated data collection and analysis. Collaboration with architects and verification teams is essential in this dynamic environment.