SoC Power & Performance Characterization Lead

Google LLC; Mountain View, San Diego (CA, CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google LLC in Mountain View, CA seeks a SoC Hardware Characterization Lead for Power and Performance to bridge custom silicon and consumer hardware software teams. You will own end-to-end post-silicon validation and drive P&P optimizations across voltage, frequency, and power-management architectures.

You will lead an engineering team, align cross-functional partners, and shape platform-level strategies to maximize SoC energy efficiency and system stability for launch-critical milestones.

Qualifications

• Bachelor's degree or equivalent practical experience in a relevant field.
• 15 years of experience with power management or low-power design/methodology.
• Experience managing the full SoC delivery cycle from architecture to post-silicon productization.
• Experience with power optimization techniques.

Responsibilities

• Own the bridging chip design, architecture, product engineering, and system software to drive power-management frameworks.
• Direct end-to-end post-silicon validation, characterization, and debugging across voltage, frequency, and power.
• Partner with engineering stakeholders to optimize manufacturing test processes and screening.
• Mentor and guide a high-performing engineering team focused on system characterization and energy efficiency.
• Drive the long-term roadmap for sensing subsystems and hardware trigger mechanisms.

Skills

Power management

Low-power design

SoC validation

Cross-functional leadership

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Google LLC in Mountain View, CA seeks a SoC Hardware Characterization Lead for Power and Performance to bridge custom silicon and consumer hardware software teams. You will own end-to-end post-silicon validation and drive P&P optimizations across voltage, frequency, and power-management architectures.

You will lead an engineering team, align cross-functional partners, and shape platform-level strategies to maximize SoC energy efficiency and system stability for launch-critical milestones.