SOC Platform Architect - IP Power

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Comprehensive benefits package

Job summary

Qualcomm in San Diego is seeking an experienced ASIC Design Engineer to join the infrastructure IP Team. The role involves working closely with HW designers to gather power estimations and analyze architectural bugs. Ideal candidates should possess strong knowledge in ASIC design and computer architecture, as well as robust communication skills.

This position offers a salary range of $140,000 to $210,000, along with a competitive bonus program and strong benefits package.

Qualifications

• 7+ years of ASIC design experience or 5+ years with a Master's degree.
• 4+ years of ASIC design experience or 3+ years with a Master's degree.
• 2+ years of ASIC design experience with a PhD.

Responsibilities

• Work with HW designers for power estimations.
• Analyze data to identify architectural bugs.
• Coordinate with domain leads on infrastructure plans.

Skills

Computer architecture

System power architecture/design

End-to-end ASIC design flows

SOC and Infrastructure IP HW architecture

Interconnect protocol

Programming for automation

Adaptability

Communication skills

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

Job Area

Engineering Group > ASICS Engineering

General Summary

The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves working with HW designer to gather power estimation of SOC Infra HW IPs, analyze the data, identify architectural and micro-architectural bugs/limitations and propose fixes and/or optimizations for the same. The ideal candidate should have a strong background in ASIC design and computer architecture while demonstrating good system level design/architecture understanding. The candidate will be required to co-ordinate with domain leads to ensure a robust infrastructure deployment plan based on product requirements. It requires understanding of HW architecture, HW‑SW feature trade-off, and the complete silicon HW end‑2‑end design flow.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, architecture, or related work experience.

Skills/Experience

• Robust understanding of computer architecture
• Experience in system power architecture/design as well as exposure to power estimation flows.
• Basic understanding of end‑end ASIC design flows
• Knowledge in SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture
• Exposure to some form of interconnect protocol
• Exposure to programming language for automation
• Ability to quickly react and adapt to changes
• Excellent communication skills

Preferred Qualification

• Exposure to Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
• Good knowledge in industry standard Interconnect Protocol and IO Devices Protocol
• Understanding of HW‑SW interfaces and firmware
• Experience in post‑silicon flows and debugs

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Equal Opportunity Employer

Qualcomm is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. The company is committed to providing accommodations for individuals with disabilities during the hiring process.

Pay and Benefits

Pay range: $140,000.00 - $210,000.00

In addition, Qualcomm offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. Benefits package designed to support success at work, at home, and at play.