SOC Limits Management Architect

Qualcomm; San Diego (CA); On-site; USD 174,000 - 262,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a SoC Limits Management Architect on the HW power team in San Diego to define how next-generation systems balance high performance with physical, electrical and thermal constraints.

You will bridge hardware IP, system software, and product requirements to design a holistic limits management architecture and collaborate with architects, designers and SW teams to evolve architecture and ROI-driven decisions.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 6+ years ASIC design/verification experience.
• Master's degree with 5+ years ASIC design/verification experience.
• PhD with 4+ years ASIC design/verification experience.

Responsibilities

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross-functional teams to standardize mitigation features across IP and hardware blocks.
• Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
• Oversee ROI-based feature decisions and Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Skills

Power management

Low-power design

Leadership

Architectural design

Product delivery cycle

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

AI

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a SoC Limits Management Architect on the HW power team, you will be responsible for defining how our next-generation systems balancing high performance against physical, electrical and thermal constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic Limits Management architecture solution. In this role, you will work with architects, designers and SW teams to conceive of the architecture and micro-architecture and help with product definition through early involvement in the product life cycle. Your work ensures our SoCs deliver maximum performance under peak current, power and thermal constraints, while maintaining long-term reliability and stability.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
• Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
• Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low-Power Design/Methodology.
• Experience navigating the full product delivery cycle, from initial architecture definition through to post-silicon productization.
• Experience with low-power architectures and advanced power optimization techniques.

Preferred qualifications:

• MS or PhD in Electronics or Computer Engineering, or equivalent, with a focus on computer architecture and power/performance analysis.
• Experience in peak power management, power budgeting, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management and AI.
• Exceptional leadership and influencing skills, with an ability to influence cross-functional roadmaps and drive ROI-based technical decisions.

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Pay range and Other Compensation & Benefits:

$174,400.00 - $261,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.