SoC Full Chip DV Engineer

Apple Inc.; Cupertino (CA); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.

You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/SystemVerilog, digital design fundamentals, and scripting (Python/Perl).

Qualifications

• BS + 3 years of relevant industry experience.
• Strong knowledge of Verilog/SystemVerilog and digital design.
• Experience with test benches, coverage, and UVM is desirable.

Responsabilités

• Verify functionality and performance of Apple’s SOCs and IPs.
• Develop and execute test plans, coverage plans, and verification methodologies.
• Run regressions, triage bugs, and analyze coverage to drive top results.

Connaissances

Verilog/SystemVerilog

C/C++

Digital design fundamentals

Python/Perl scripting

Independent work

Formation

BS + 3 years experience

Description du poste

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new insights have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what we'll could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology, and we'd love to have you join us.

Description

As part of a very talented team, we are at the heart of the chip design effort collaborating with all fields (vertical product model)! You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans; tests & coverage plans as well as define our next generation verification methodology & test benches. It’s required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.

Minimum Qualifications

• Minimum of BS + 3 years relevant industry experience.

Preferred Qualifications

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
• Knowledge of Verilog/SystemVerilog, digital simulation and debug
• Knowledge of computer architecture and digital design fundamentals
• Ability to work independently to deliver the project goals
• Exposure to UVM is desired
• Experience with C/C++, assembly is a plus
• Experience with perl, python or similar scripting language
• Excellent interpersonal skills and the dream to take on diverse challenges

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Learn about accessibility in Apple’s workplace
Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.