SoC Physical Design Engineer, PnR

Apple Inc.; Waltham (MA); On-site; USD 80,000 - 120,000; Full time

Job summary

An established industry player is seeking a SoC Physical Design Engineer to join their innovative team. In this role, you will collaborate closely with architecture, CAD, and design teams to create cutting-edge designs that will shape the future of technology. You'll be responsible for driving the physical design process, from netlist implementation to verification, ensuring that all projects meet rigorous standards and deadlines. This is a fantastic opportunity for someone with a foundational understanding of logic design and a passion for teamwork, looking to make a significant impact in a dynamic environment. Join us to help build the next generation of hardware solutions!

Qualifications

• Basic understanding of logic gates is required.
• Internship or project work in VLSI or circuit design is preferred.

Responsibilities

• Collaborate with teams to drive physical aspects early in design.
• Complete netlist to GDS2 implementation meeting design goals.
• Conduct timing and physical verification for design signoff.

Skills

Logic Gates Understanding

Teamwork Skills

Verilog

VHDL

Python

Perl

TCL

SPICE

Education

Computer Architecture Coursework

VLSI Design Coursework

Circuit Design Coursework

Job description

Waltham, Massachusetts, United States Hardware

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Description

In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs. Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include:

1. Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
2. Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
3. Timing, physical and electrical verification, and driving the signoff closure for the partitions.
4. Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

• Basic understanding of logic gates.

Preferred Qualifications

• Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields.
• Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.