SoC Performance & QoS Architect — Interconnect & Memory

Apple; Austin (TX); On-site; USD 170,000 - 250,000; Full time

Job summary

Apple in Austin seeks an energetic SoC performance engineer to help shape on-chip interconnect and memory QoS. You will help create a full-chip C++ simulator for iPhone/iPad/Mac/Watch SoCs, modeling emerging workloads like AR and ML, and evaluating performance and power trade-offs across architectures.

Join a fast-moving Platform Architecture team; you will study problems in depth, design experiments, analyze data, and present results to drive architecture improvements.

Qualifications

• BS degree required.
• Experience with C++ and performance modeling.
• Strong understanding of HW/SW stack.
• Experience with debugging performance issues.

Responsibilities

• Develop full-chip C++ simulator for SoCs.
• Model AR/ML workloads and new traffic patterns.
• Study performance and power trade-offs across architectures.
• Collaborate with hardware and software teams to drive architecture improvements.

Skills

BS degree

C++ programming experience

Computer architecture

Performance modeling

Education

BS degree

Job description

Apple in Austin seeks an energetic SoC performance engineer to help shape on-chip interconnect and memory QoS. You will help create a full-chip C++ simulator for iPhone/iPad/Mac/Watch SoCs, modeling emerging workloads like AR and ML, and evaluating performance and power trade-offs across architectures.

Join a fast-moving Platform Architecture team; you will study problems in depth, design experiments, analyze data, and present results to drive architecture improvements.