SoC Performance Architect for AI Wearables

Meta

Redmond (WA)

On-site

USD 178,000 - 250,000

Full time

32 hours ago
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Job summary

Meta's Reality Labs is seeking a Silicon Performance Architect to lead performance modeling, correlation, workload profiling, and analysis for custom SoCs powering AI-enabled wearables. You will drive bottleneck analysis and develop models of IPs, fabric, and DRAM to guide design choices.

Based in Redmond, WA, you will collaborate with hardware teams and vendors, create micro-benchmarks, and document findings for cross-functional partners.

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, or equivalent.
  • 8+ years creating performance models with C/C++ or SystemC.
  • Experience with SoC architecture, NoCs, memory sub-system, QoS, and heterogeneous compute principles.
  • Experience with scripting, infrastructure, automation, and visualization using Python.
  • Experience with power concepts and trade-offs.
  • Ability to document analyses for peers and cross-functional partners.

Responsibilities

  • Conduct bottleneck analysis of existing and future SoCs to identify areas for improvement.
  • Develop accurate models of IP components, SoC fabric, and DRAM to predict performance and inform design decisions.
  • Analyze system usage behavior of workloads and create micro-benchmarks to evaluate performance.
  • Identify opportunities for optimization and collaborate with hardware teams to solidify HW-SW co-design.
  • Work across disciplines, collaborate with vendors, brainstorm ideas and solutions, develop new methodologies, and coordinate multiple initiatives.

Skills

C/C++
SystemC
Python
SoC architecture
Power concepts

Education

Bachelor's degree in Computer Science/Engineering

Tools

SystemC

Job description

Meta's Reality Labs is seeking a Silicon Performance Architect to lead performance modeling, correlation, workload profiling, and analysis for custom SoCs powering AI-enabled wearables. You will drive bottleneck analysis and develop models of IPs, fabric, and DRAM to guide design choices.

Based in Redmond, WA, you will collaborate with hardware teams and vendors, create micro-benchmarks, and document findings for cross-functional partners.

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