SoC Memory Power Lead — PPA Optimizer for Mobile SoCs

Google

Mountain View (CA)

On-site

USD 192,000 - 278,000

Full time

14 days+
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Job summary

Google is seeking a senior SoC Power Architect to lead memory subsystem power requirements and optimization across Tensor mobile SoCs. You will collaborate with hardware, software, and verification teams to ensure optimal energy efficiency and performance in mass-produced devices.

You will influence power-performance trade-offs, drive cross-functional initiatives, and report progress to senior leadership while shaping the future of Google's silicon strategy.

Qualifications

  • Bachelor's degree or equivalent practical experience in EE/CS.
  • 10+ years of memory subsystem architectures experience.
  • Experience in power management and low power design/methodology.
  • Experience with full product delivery cycle (definition, architecture, design and implementation, testing, productization).

Responsibilities

  • Lead the definition of power requirements for Tensor mobile SoCs to achieve Power-Performance-Area with focus on memory subsystem.
  • Own and drive cross-functional teams to deliver power KPIs for memory subsystem and other major SoC IPs.
  • Propose and drive power optimizations for memory subsystem throughout the design process from concept to mass productization.
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
  • Represent status of SoC power to the executive leadership team.

Skills

Memory subsystem architectures
Power management
SoC design experience
Cross-functional leadership
Product delivery lifecycle

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree or PhD with emphasis on computer architecture

Job description

Google is seeking a senior SoC Power Architect to lead memory subsystem power requirements and optimization across Tensor mobile SoCs. You will collaborate with hardware, software, and verification teams to ensure optimal energy efficiency and performance in mass-produced devices.

You will influence power-performance trade-offs, drive cross-functional initiatives, and report progress to senior leadership while shaping the future of Google's silicon strategy.

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