SoC Engineer

OpenAI; United States; Remote; USD 120,000 - 180,000; Full time

Job summary

OpenAI’s Hardware team is seeking a SoC Engineer to architect, design, and integrate OpenAI’s first‑party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects accelerators into complete systems, collaborating with design, architecture, verification, and software teams across development stages.

You will define subsystem requirements, integrate IP, and contribute to pre‑silicon validation, silicon bring‑up, and post‑silicon debugging.

Job description

About the Team

OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands‑on engineering, and creative approaches to building complex hardware.

About the Role

We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands‑on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre‑silicon validation, silicon bring‑up, and post‑silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end.

In this role, you will:

• Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die‑to‑die interfaces.
• Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality.
• Integrate Arm Cortex‑M and Cortex‑A processors, AXI/APB fabrics, and third‑party controller IP, including the RTL and glue logic needed to connect these components.
• Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior.
• Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure.
• Drive PCIe and other I/O integration, including controller and PHY interfaces, high‑speed SerDes,