SoC DRAM Memory Subsystem Validation Engineering Program Manager

Socket.dev; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple is seeking a Program Manager for the SoC DRAM Memory Subsystem Validation and Debug to drive readiness for our custom SoCs. You will oversee bring-up, validation, and debugging of high‑bandwidth memory subsystems, interfacing with DRAM architecture, Memory Controller Design, DV, DDR PHY, DRAM product engineering, and software teams.

This role fuels the DRAM roadmap and directs teams to deliver memory technologies from architecture to mass production, upholding Apple’s renowned quality

Qualifications

• BS degree and 10+ years of relevant experience.
• Experience in SOC DRAM memory design, validation, architecture or test/product engineering.
• Strong collaboration with cross-functional teams.

Responsibilities

• Drive memory subsystem bring-up, validation, and complex debugging for Apple’s SoCs.
• Coordinate with DRAM architecture, Memory Controller Design, DV, DDR PHY, DRAM product engineering, and software teams to deliver memory technologies.
• Help craft the DRAM roadmap and drive technologies from architecture to mass production while meeting Apple’s quality standards.

Skills

SOC DRAM Memory Design

Validation

Architecture

Test/Product Engineering

Education

BS

Job description

Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years and very significant R&D spending. To make the best use of those employees, time, and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world!

Description

The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.

Minimum Qualifications

BS + 10 years of relevant experiencePrior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering.

Preferred Qualifications

• Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms.
• Experience shipping high volume DRAMs / SoCs.
• Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus.
• Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management.
• Excellent debugging skills.
• Proven track record to drive resolution of critical problems, while under pressure.
• Ability to understand complex technical discussions and extract action plans.
• Passionate to own/drive project development using well-defined metrics.
• Thrives in dynamic schedule driven development environment.
• Ability to succinctly summarize complex details for executive reporting.
• Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picturePhenomenal leadership and social skills with a reciprocal approach.