SOC/ASIC Physical Design Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Sunnyvale (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

Join a forward-thinking company at the forefront of space technology as a SOC/ASIC Physical Design Engineer. In this dynamic role, you will collaborate with top-tier engineers to develop next-generation ASICs that enhance connectivity for the world’s largest satellite constellation. Your expertise will help drive innovations that expand the capabilities of a groundbreaking broadband internet system, impacting communities and businesses globally. This is an exciting opportunity to contribute to cutting-edge projects in a fast-paced environment, where your skills will directly influence the future of connectivity in space and on Earth.

Benefits

Comprehensive medical coverage

Vision and dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation

Paid holidays

Sick leave

Employee Stock Purchase Plan

Long-term cash awards

Discretionary bonuses

Qualifications

• 1+ years of experience with ASICs and physical design flow.
• Bachelor’s degree in relevant engineering or computer science field.

Responsibilities

• Perform physical implementation steps including synthesis and timing checks.
• Develop methodologies and automation scripts for design processes.
• Collaborate with ASIC design team on architectural feasibility.

Skills

ASIC Design

Physical Design Flow Development

Scripting Skills (csh/bash, Perl, Python, TCL, Makefile)

Collaboration Skills

Problem-Solving

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Bachelor’s degree in Computer Science

Tools

EDA Tools

Job description

SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 1+ years of professional experience working with ASICs and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Basic experience of ASIC/SOCs RTL2GDSII physical design and signoff flows
• Basic experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:

Pay range:
Physical Design Engineer/Level I: $130,000.00 - $155,000.00/per year
Physical Design Engineer/Level II: $150,000.00 - $180,000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.