Director, System Level Testing - Product Development Engineering

NVIDIA; Santa Clara (CA); On-site; USD 272,000 - 426,000; Full time

Job summary

NVIDIA seeks an experienced Director of System Level Testing to lead post-silicon validation, test architecture, and manufacturing ramp for AI, data center, SOC, and Tegra Automotive lines.

You will guide a team responsible for bringing next-generation GPU/SOC/LPU/Auto/Tegra technologies from design validation through manufacturing ramp and high-volume production, collaborating across design, test, reliability, and manufacturing teams.

Qualifications

• Master’s or Ph.D. in Electrical Engineering, Physics, Computer Engineering, or a related field, or equivalent experience.
• 15+ years of semiconductor product development, testing or manufacturing engineering with leadership experience.
• 5+ years of Director leadership or management experience leading engineering teams.
• Strong understanding of CMOS, component characterization, and analog/mixed-signal circuit behavior.
• Experience with high-speed testing and characterization.
• Proven experience in yield analysis, product characterization, and silicon debugging.
• Experience using statistical data analysis tools (e.g., JMP) for engineering insights and yield improvement.
• Demonstrated ability to drive cross-functional problem solving under aggressive schedules.
• Strong leadership, communication, and organizational skills.

Responsibilities

• Lead and mentor a team of product development engineers responsible for validation, characterization, and production ramp of NVIDIA product lines.
• Drive product development strategy from early silicon validation through qualification and high-volume manufacturing.
• Develop and implement validation methodologies and test strategies for mixed-signal silicon designs.
• Partner closely with Mixed-Signal Design, Test Engineering, Reliability, and Manufacturing teams to ensure seamless transition from design to production.
• Oversee Product characterization of new integrated circuit designs.
• Lead root-cause analysis and complex problem resolution related to silicon performance, yield excursions, and product reliability.
• Drive yield improvement initiatives, test time reduction, and manufacturing efficiency across wafer and module test flows.
• Provide structured feedback to design teams regarding silicon performance, design margins, and manufacturability improvements.
• Establish scalable data analysis frameworks, automation tools, and statistical methodologies for validation and production monitoring.
• Collaborate with operations teams to support product qualification, ramp readiness, and high-volume manufacturing scaling.

Skills

Technical leadership

System level testing

CMOS understanding

High-speed testing

Yield analysis

Statistical data analysis (JMP)

Education

Master’s or Ph.D. in Electrical Engineering / Physics / Computer Engineering

Tools

JMP

Job description

NVIDIA is seeking an experienced and highly motivatedDirector of System level Testing to lead the end-to-end post-silicon validation, test architecture, and manufacturing ramp for cutting-edge AI, data center, SOC and Tegra Automotive product lines. In this leadership role, you will guide a team responsible for bringing next-generation GPU/SOC/LPU/Auto/Tegra technologies from design validation through manufacturing ramp and high-volume production.

You will collaborate across design, Silicon Co-design Group, test engineering, reliability, and manufacturing teams to driveyield improvement, test optimization. The ideal candidate combines strongtechnical depth in CMOS, System Level testing and mixed-signal systemswith provenleadership in product development and high-volume semiconductor manufacturing.

What You'll Be Doing:

• Lead and mentor ateam of product development engineersresponsible for validation, characterization, and production ramp of NVIDIA product lines.

• Driveproduct development strategyfrom early silicon validation through qualification and high-volume manufacturing.

• Develop and implementvalidation methodologies and test strategiesfor mixed-signal silicon designs.

• Partner closely withMixed-Signal Design, Test Engineering, Reliability, and Manufacturing teamsto ensure seamless transition from design to production.

• OverseeProduct characterizationof new integrated circuit designs.

• Leadroot-cause analysis and complex problem resolutionrelated to silicon performance, yield excursions, and product reliability.

• Driveyield improvement initiatives, test time reduction, and manufacturing efficiencyacross wafer and module test flows.

• Provide structured feedback to design teams regardingsilicon performance, design margins, and manufacturability improvements.

• Establish scalabledata analysis frameworks, automation tools, and statistical methodologiesfor validation and production monitoring.

• Collaborate with operations teams to supportproduct qualification, ramp readiness, and high-volume manufacturing scaling.

What We Need to See:

• Master’s or Ph.D. inElectrical Engineering, Physics, Computer Engineering, or a related field, or equivalent experience.

• 15+ years of background in semiconductor product development, testing or manufacturing engineering, including significant leading large, cross-functional technical teams.

• 5+ years of Director leadership or management experienceleading engineering teams.

• Strong understanding ofCMOS, Component characterization, and analog/mixed-signal circuit behavior.

• Experience withhigh-speed testing, and characterization

• Proven experience inyield analysis, product characterization, and silicon debug.

• Experience usingstatistical data analysis tools (e.g., JMP)for engineering insights and yield improvement.

• Demonstrated ability todrive cross-functional problem solving under aggressive schedules.

• Strong leadership, communication, and organizational skills.

Ways to Stand Out From the Crowd:

• Experience developing or productizingSOC, GPU, Automotive

• Deep expertise inSystem Level testing, Voltage-Frequency understanding and manufacturing ramp readiness.

• Experience withcontrol loops, feedback systems, and high-speed SerDes/analog front-end validation.

• Deep knowledge of advanced CMOS process technologies, multi-chip module (MCM) and high speed interfaces

• Experience leadingproduct ramps from prototype to high-volume manufacturing.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. This role presents an opportunity to have a wide impact at NVIDIA by improving the factory planning function. Are you creative, hard-working, dedicated, and determined? Do you love a challenge? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 425,500 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 1, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.