Silicon PDE for GPU Data Center Yields & Test

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 213,000; Full time

Job summary

NVIDIA seeks a Silicon Product Development Engineer to lead ATE test content development for new Data Center silicon products. You will influence GPU production yields, forecast test times, and drive characterization outcomes to improve quality and performance.

The role requires 5+ years PDE experience, strong problem-solving, and hands-on expertise in ASIC mixed-signal, BIST/SCAN DFT, and FinFET processes, with Semiconductor assembly and HBM vendor management experience.

Qualifications

• Bachelor or Master in Electrical Engineering or equivalent experience.
• 5+ years of PDE experience.
• Strong problem-solving skills and track record in ASIC mixed signal build, characterization, and qualification of BIST and SCAN DFT methodologies.
• Knowledgeable in advanced silicon process technology such as FinFET.
• Hands-on experience in Chip-On-Wafer-On-Substrate Assembly, Silicon GPU Product Engineering, and HBM memory vendor management.

Responsibilities

• Own the development and implementation of ATE test content for the product line.
• Impact GPU manufacturing yields and predict test durations by analyzing characterization outcomes.
• Develop and maintain failure analysis plans to drive yield improvement.
• Manage key vendor relationships with Foundry, Assembly, and Memory vendors.
• Collaborate with Supply and Demand program management to meet chip quality goals.

Skills

Problem-solving

Interpersonal collaboration

ASIC mixed signal knowledge

BIST/SCAN DFT knowledge

Education

Bachelor's in Electrical/Computer Engineering

Master's in Electrical/Computer Engineering

Tools

FinFET

Chip-On-Wafer-On-Substrate Assembly

HBM memory vendor management

BIST

Job description

NVIDIA seeks a Silicon Product Development Engineer to lead ATE test content development for new Data Center silicon products. You will influence GPU production yields, forecast test times, and drive characterization outcomes to improve quality and performance.

The role requires 5+ years PDE experience, strong problem-solving, and hands-on expertise in ASIC mixed-signal, BIST/SCAN DFT, and FinFET processes, with Semiconductor assembly and HBM vendor management experience.