GPU Silicon Test & Yield Engineer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 213,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA seeks a Silicon Product Development Engineer to help launch new Data Center products, improve GPU yields, and optimize test time forecasts. You will own ATE test content development, coordinate with Foundry, Assembly, and Memory vendors, and drive yield improvement through advanced characterization.

Preferred candidates hold a bachelor's or master's in Electrical/Computer Engineering with 5+ years PDE experience, FinFET knowledge, and hands-on silicon assembly expertise.

Qualifications

• 5+ years of PDE experience required.
• Strong problem solving for ASIC Mixed Signal build, characterization, and qualification of BIST/SCAN DFT.
• Knowledge of FinFET silicon process technology.
• Hands-on experience with Chip-On-Wafer-On-Substrate assembly and silicon GPU product engineering.

Responsibilities

• Own the development and implementation of ATE test content for our product line.
• Impact GPU manufacturing yields, minimize excess, and predict test durations and characterization outcomes.
• Develop and maintain failure analysis plans to improve yield.
• Manage vendor relationships with Foundry, Assembly, and Memory vendors.
• Collaborate with Supply and Demand program management to meet chip quality levels.

Skills

PDE experience

BIST/SCAN DFT

FinFET

Chip-on-Wafer-On-Substrate

Silicon GPU engineering

Vendor management

Education

Bachelor's or Master’s degree in Electrical/Computer Engineering

Job description

NVIDIA seeks a Silicon Product Development Engineer to help launch new Data Center products, improve GPU yields, and optimize test time forecasts. You will own ATE test content development, coordinate with Foundry, Assembly, and Memory vendors, and drive yield improvement through advanced characterization.

Preferred candidates hold a bachelor's or master's in Electrical/Computer Engineering with 5+ years PDE experience, FinFET knowledge, and hands-on silicon assembly expertise.