Silicon-First AI Model Architect

Ericsson GmbH; Austin, Northern (TX, KY); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

401(k) with company match

Paid time off

Maternity/paternity leave

Stock Purchase Plan

Job summary

Ericsson Austin is seeking an AI Model Architect to bridge the gap between cutting-edge transformer models and ASIC design. You will define partitioning and tiling, map models to heterogeneous compute fabrics, and guard the canonical results in JAX and PyTorch while validating with cycle-accurate simulators.

You will shape model-to-hardware translation, project performance ahead of RTL, and work with SDK teams to ensure research intent becomes real silicon behavior.

Qualifications

• Deep knowledge of Transformer architectures and how they map to hardware execution profiles.
• Experience in hardware-in-the-loop optimization and memory hierarchy considerations.
• Proficiency in JAX, PyTorch, or TensorFlow for export/compilation and graph capture.

Responsibilities

• Translate AI and RAN algorithms into precise hardware specifications for ASICs and SDK lowering.
• Define strategies to decompose large models for heterogeneous compute fabrics with tiling and dataflow.
• Own canonical reference implementations in JAX and PyTorch and ensure bit-for-bit alignment with silicon.
• Project performance with cycle-accurate simulators and SystemC models before RTL is written.
• Collaborate with SDK team to ensure intended math maps to hardware execution.

Skills

Transformer architectures

Hardware-aware ML

JAX

PyTorch

TensorFlow

SystemC simulation

XLA compilation

StableHLO representations

RAN AI workloads

Numerical precision & fixed-point

Tools

SystemC

MLIR

XLA

Job description

Ericsson Austin is seeking an AI Model Architect to bridge the gap between cutting-edge transformer models and ASIC design. You will define partitioning and tiling, map models to heterogeneous compute fabrics, and guard the canonical results in JAX and PyTorch while validating with cycle-accurate simulators.

You will shape model-to-hardware translation, project performance ahead of RTL, and work with SDK teams to ensure research intent becomes real silicon behavior.