AI Systems Engineer: Model-to-Silicon Optimization

Unconventional AI; Mountain View (CA); On-site; USD 180,000 - 290,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals

Job summary

Unconventional AI is seeking a Member of Technical Staff, AI Systems, Model Optimization, to drive the path from model architecture to silicon. You will develop training techniques, optimizations, and infrastructure to run AI models efficiently on novel compute substrates, linking model design to tapeouts.

You will implement energy benchmarks, partitioning strategies, and quantization schemes while collaborating with hardware teams to translate requirements into concrete specs for tapeouts.

Qualifications

• MS/PhD or equivalent in AI/CS/Physics/Electrical Engineering or Applied Math.
• Deep, practical understanding of the modern AI/ML stack and optimized compilation on GPUs.
• Map state-of-the-art AI models to system performance and apply efficiency techniques.

Responsibilities

• Develop energy benchmarks and performance models for compute, memory, and energy trade-offs.
• Partition and map AI models to hardware with advanced optimization strategies.
• Develop and apply QAT, noise-aware training, and sparsification to fit substrates.
• Develop and optimize kernels using CUDA, Triton, or CUTLASS and debug ML codebases.
• Collaborate with AI model architects and hardware teams for tapeouts.

Skills

AI/ML fundamentals

GPU optimization

Performance profiling

Cross-functional collaboration

Education

MS/PhD in AI/CS/Physics/EE/Applied Math

Tools

PyTorch

Torch.compile

DDP

FSDP

CUDA

Triton

CUTLASS

Job description

Unconventional AI is seeking a Member of Technical Staff, AI Systems, Model Optimization, to drive the path from model architecture to silicon. You will develop training techniques, optimizations, and infrastructure to run AI models efficiently on novel compute substrates, linking model design to tapeouts.

You will implement energy benchmarks, partitioning strategies, and quantization schemes while collaborating with hardware teams to translate requirements into concrete specs for tapeouts.