Silicon Diagnosis DFT Engineer

AMD; San Jose (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

AMD is seeking a diagnose expert with scan DFT knowledge to enhance debug capabilities. You will generate diagnosis patterns and collaborate with design, verification, test engineering, and yield analysis groups to isolate faults.

In this PMTS role, you will build diagnosis patterns, automate volume diagnosis, and work with DFX teams to create diagnosable designs, contributing to broader AI/compute innovations. San Jose, CA location.

Qualifications

• Post-silicon fault isolation expertise required.
• 2

Responsibilities

• Perform post-silicon electrical/physical fault isolation.
• 3

Skills

C/C++

Verilog

Scripting

Education

Electrical Engineering degree

Knowledge of IC design/verification/DFT

Tools

Xilinx Vivado

VCS

Caliber

Primetime

FPGA design tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

Looking for a diagnose expert, with scan DFT knowledge, to improve/enhance debug and diagnosis capabilities and implement features to meet new diagnosis challenges. In the role of a PMTS, you will conduct electrical/physical fault isolation by generating diagnosis patterns and collaborating with design, verification, test engineering, and yield analysis groups.

The Person

Proficient in IC design/automation, silicon product validation, characterization, or debug/diagnosis, in particular using scan DFT techniques. Experiences of using commercial tools for ATPG and pattern validations. Have strong problem solving, communication, and teamwork skills. Motivated and proactive, willing to adapt and learn new techniques.

Key Responsibilities

• Perform post-silicon electrical/physical fault isolation.
• Work with verification and test team to make diagnosable tests.
• Build layout databases for diagnosis and cross-probing.
• Generate scan diagnosis tests for fault isolation.
• Automate volume diagnosis and data analysis.
• Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging.
• Work with design and DFX team for diagnosable designs.

Preferred Experience

• Familiar with C/C++ or Verilog
• Fluent in scripting (Perl/Python/TCL)
• Experience in IC process technology, ATE, yield analysis or memory design, layout design, FPGA design tools (Xilinx Vivado) or any validation tools (VCS, Caliber, Primetime).

Academic Credentials

Degrees in Electrical Engineering, with knowledge of IC design/verification/DFT (RTL, circuit, physical), and semiconductor physics.

LOCATION: San Jose, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s "Responsible AI Policy" is available here.

This posting is for an existing vacancy.