Silicon Diagnosis DFT Engineer

AMD; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

AMD in San Jose seeks a diagnose expert with scan DFT knowledge to improve debug and diagnosis capabilities. In the PMTS role, you will conduct electrical/physical fault isolation by generating diagnosis patterns and collaborating with design, verification, test engineering, and yield analysis groups.

You should be proficient in IC design/automation, silicon product validation or debug/diagnosis, with experience using commercial ATPG/pattern validation tools.

Qualifications

• Experience in IC design/verification/DFT (RTL, circuit, physical).
• Knowledge of semiconductor physics and IC integration.
• Experience with scan DFT techniques and diagnosis patterns.

Responsibilities

• Perform post-silicon electrical/physical fault isolation.

Skills

C/C++

Verilog

Perl

Python

TCL

Problem solving

Communication

Teamwork

Education

Electrical Engineering degree

Tools

Xilinx Vivado

VCS

Caliber

Primetime

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

Looking for a diagnose expert, with scan DFT knowledge, to improve/enhance debug and diagnosis capabilities and implement features to meet new diagnosis challenges.In the role of a PMTS, you will conduct electrical/physical fault isolation by generating diagnosis patterns and collaborating with design, verification, test engineering, and yield analysis groups.

THE PERSON:

Proficient in IC design/automation, silicon product validation, characterization, or debug/diagnosis, in particular using scan DFT techniques. Experiences of using commercial tools for ATPG and pattern validations. Have strong problem solving, communication, and teamwork skills. Motivated and proactive, willing to adapt and learn new techniques.

KEY RESPONSIBILITIES:

• Perform post-silicon electrical/physical fault isolation.
• Work with verification and test team to make diagnosable tests.
• Build layout databases for diagnosis and cross-probing.
• Generate scan diagnosis tests for fault isolation.
• Automate volume diagnosis and data analysis.
• Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging.
• Work with design and DFX team for diagnosable designs.

PREFERRED EXPERIENCE:

• Familiar with C/C++ or Verilog
• Fluent in scripting (Perl/Python/TCL)
• Experience in IC process technology, ATE, yield analysis or memory design, layout design, FPGA design tools (Xilinx Vivado) or any validation tools (VCS, Caliber, Primetime).

ACADEMIC CREDENTIALS:

Degrees in Electrical Engineering, with knowledge of IC design/verification/DFT (RTL, circuit, physical), and semiconductor physics.

LOCATION:

San Jose, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.