Silicon Design Engineer

Persimmons, Inc.; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive salary

Flexible PTO

401k

Job summary

Persimmons, Inc. is seeking a Silicon Design Engineer in San Jose to deliver high-quality RTL-to-PD with PD Partners, focusing on meeting timing, power, and area targets.

You will collaborate with RTL, DFT, and verification teams, run STA, create timing constraints, and develop automated design flows using Cadence/Synopsys tools and AI-assisted automation to accelerate iterations.

Qualifications

• 3+ years of RTL-to-PD implementation experience through tapeout on real silicon.
• Proficiency in SystemVerilog/Verilog and Cadence/Synopsys toolchains.
• Ability to write timing constraints from RTL understanding and solve STA issues.

Responsibilities

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks.
• Drive timing closure by authoring precise timing constraints and resolving setup violations across multi-corner environments.
• Execute floorplanning and physical implementation using Cadence/Synopsys tools for optimized PPA.
• Build and maintain scripted, automated design flows to accelerate iteration and reduce manual overhead.
• Collaborate with RTL, DFT, and verification teams to manage frontend-to-backend handoffs and ensure quality checks.
• Contribute to post-DV design activities such as power analysis, CDC/RDC checks, UPF creation, and MBIST integration.

Skills

SystemVerilog/Verilog

Static timing analysis

Timing constraints from RTL

Scripting & automation flows

AI-assisted automation

Education

Bachelor’s or Master’s degree in EE/CE

Tools

Cadence

Synopsys

Job description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.

Why join us:

We’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you’re ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you’ll do:

As a Persimmons Silicon Design Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
• Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
• Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
• Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes—leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
• Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
• Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.

What You Bring To The Table:

• Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
• Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
• Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
• Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.
• Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).

• Competitive salary and benefits package
• Flexible PTO
• 401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.