Principal Debug Validation Engineer

Graphcore; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

Graphcore in Austin, TX, is seeking a Principal Embedded SW/FW Engineer to support new product introductions in AI technology. In this critical role, you will validate cutting-edge silicon and provide technical direction to ensure quality product launches.

Your responsibilities will include developing and deploying validation tests, collaborating across functions, and building an automated test framework in Python. Candidates should have 5 to 10 years of experience and strong skills in embedded C/C++.

Qualifications

• 5 to 10 years of experience in embedded systems.
• Ability to work across teams and programming languages.
• Experience with Ethernet and memory technologies.

Responsibilities

• Plan, design, develop and debug silicon validation tests.
• Deploy silicon validation tests on first silicon.
• Develop an automated test framework in Python.

Skills

Bare metal / embedded C/C++

Problem-solving

Analytical skills

Communication skills

Experience of post-silicon validation process

Understanding of ML applications

Tools

FPGA/Emulator

Python

Debug tools

Job description

Principal Embedded SW/FW Engineer (Bringup) – Austin, TX, USA

Job Summary

We have an exciting opportunity to be part of a collaborative, cross‑functional development team validating cutting‑edge, high‑performance AI chips and platforms. You will play a key role in supporting new product introductions and post‑silicon validation. Working within the Post‑Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members, and to architect and drive implementation of continuous improvements to test infrastructure and processes.

Responsibilities and Duties

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy silicon validation tests on first silicon and debug them
• Develop an automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile

• Understanding of ML applications and their workloads
• A self‑starter who can apply independent judgement
• A team player able to lead and support colleagues with difficult concepts
• Strong experience in Bare metal / embedded C/C++
• Excellent problem‑solving, analytical & diagnostic skills
• Ability to work across teams and programming languages to find root causes of critical and complex issues
• Experience of the post‑silicon validation process applied in digital ASIC environments
• Excellent communication skills and the ability to explain difficult concepts to resolve issues
• 5 to 10 years’ experience
• Experience building and leading multi‑site teams
• Driver level experience with one or more of the following is highly desirable:
• Ethernet
• Memory technologies (LPDDR, DDR, HBM)
• Other peripherals such as I2C, I3C, SPI
• Good knowledge of mixed‑signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis

The Team

The Post‑Silicon Bringup team sits within the Architecture and Validation team; we are responsible for bring‑up and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.