Signal & Power Integrity Engineer — Innovate High-Speed HW

Apple; Cupertino (CA); On-site; USD 95,000 - 135,000; Full time

Job summary

Apple is seeking an early career signal and power integrity (SI/PI) engineer in Cupertino to support architectural exploration and product development. The role emphasizes SI/PI for high-speed links (PCIe, USB, DP, MIPI) and low-speed buses, plus PDN analysis.

You will work with cross-functional teams to define I/O and power architecture, triage SI/PI issues during validation, and help deploy SI/PI test methodologies across manufacturing.

Qualifications

• BS/MS/PhD in EE or equivalent.
• Solid EE fundamentals and problem solving.
• Knowledge of high-speed and low-speed I/O interfaces.
• Power integrity modeling, simulation, and lab correlation.
• Familiarity with DC-DC regulator design principles, modeling, and troubleshooting.
• Proficiency with SI/PI simulation tools (Cadence/Sigrity, ADS/Spice, Ansys HFSS, CST).
• Strong programming background is a plus.
• Hands-on hardware characterization, validation, and failure analysis with lab equipment.

Responsibilities

• System-level SI simulation and design evaluation, including PCB stackup, placement/routing, and IO selection.
• System-level PI simulation and design evaluation, including power/ground plane optimization and decoupling strategies.
• Define IO and power architecture and silicon/module/interconnect specs with cross-functional teams.
• Triage, debug, root cause, and fix SI/PI issues in product integration with validation teams.
• Develop and deploy SI/PI focused factory test methodologies and flows.

Skills

SI/PI engineering

High-speed interfaces

Power integrity

PCB design knowledge

Programming basics

Education

BS/MS/PhD in EE or equivalent

Tools

Cadence/Sigrity

ADS/Spice

Ansys HFSS

CST

Job description

Apple is seeking an early career signal and power integrity (SI/PI) engineer in Cupertino to support architectural exploration and product development. The role emphasizes SI/PI for high-speed links (PCIe, USB, DP, MIPI) and low-speed buses, plus PDN analysis.

You will work with cross-functional teams to define I/O and power architecture, triage SI/PI issues during validation, and help deploy SI/PI test methodologies across manufacturing.