Signal and Power Integrity Technical Leader (Remote)

Ladders; United States; Remote; USD 214,000 - 310,000; Full time

Benefits offered by this job

Flexible remote work options

Leadership role in a high-impact team

Access to advanced technology and tool

Professional development opportunities

Collaborative culture of innovation

Job summary

Ladders is seeking a Signal and Power Integrity Technical Leader (Remote) to guide ASIC packaging and SI efforts for high-speed hardware. You will lead a specialized engineering team, collaborate with layout and vendor teams, and mentor engineers in a highly collaborative environment.

The role involves shaping technical processes, reviewing intricate IC designs, and driving design rules to meet demanding power and performance targets. This is a remote US-based opportunity.

Qualifications

• Bachelor’s degree in Electrical Engineering with 10+ years of experience in signal/power integrity.
• Proven track record with multiple high-speed ASIC tape-outs from packaging perspective.
• In-depth knowledge of 56G PAM4 and high-speed SerDes architectures, channel modeling and transmission line theory.
• Hands-on experience with layout review using Keysight ADS, Ansys HFSS/EM flow, and Cadence APD.
• Familiarity with SPICE for circuit simulation.

Responsibilities

• Lead the development of next-generation ASIC packaging and manage the Signal and Power Integrity team.
• Implement design rules for ultra-high-speed signaling to meet power and performance goals.
• Analyze substrate signal and power integrity, collaborating with layout teams to develop optimal solutions.
• Design and document ASIC packages for high-volume production, including post-layout extraction.
• Collaborate with system partners and vendors to resolve complex technical issues using advanced design rules.
• Define processes and tools for complex ASIC/package development.
• Participate in chip architecture discussions and review intricate IC designs.
• Mentor junior engineers and promote a culture of continuous improvement across engineering teams.

Skills

Signal integrity

Power integrity

Technical leadership

Mentoring

ASIC packaging

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

For our client, we are seeking a Signal and Power Integrity Technical Leader (Remote) to join the team of a leader in the Telecommunications & Hardware space.

This role will guide advanced ASIC packaging and signal integrity efforts for complex, high-speed hardware solutions. The individual will lead a specialized engineering team, partner closely with layout, system, and vendor teams, and help ensure designs meet demanding performance and power targets. This position also plays an important role in shaping technical processes, reviewing intricate IC designs, and mentoring engineers in a highly collaborative environment.

Location: Remote - US based candidates only, no visa sponsorship available

Compensation: $214,100 – $309,800 annually

Responsibilities

• Lead the development of next-generation ASIC packaging and manage the Signal and Power Integrity team.
• Implement design rules for ultra-high-speed signaling to meet power and performance goals.
• Analyze substrate signal and power integrity, collaborating with layout teams to develop optimal solutions.
• Design and document ASIC packages for high-volume production, including post-layout extraction.
• Collaborate with system partners and vendors to resolve complex technical issues using advanced design rules.
• Define processes and tools for complex ASIC/package development.
• Participate in chip architecture discussions and review intricate IC designs.
• Mentor junior engineers and promote a culture of continuous improvement across engineering teams.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of experience, or Master's degree with 8+ years, or PhD with 5+ years in signal/power integrity.
• Proven track record with multiple high-speed ASIC tape-outs from a packaging perspective.
• In-depth knowledge of 56G PAM4 and high-speed SerDes architectures, including channel modeling and transmission line theory.
• Hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Familiarity with SPICE for circuit simulation.

Benefits

• Flexible work options, including the possibility of fully remote work.
• Opportunity to lead and influence a high-impact technical team.
• Access to advanced technology and tools in a cutting-edge environment.
• Support for professional development and continuous learning.
• Collaborative culture that encourages innovation and technical excellence.

Our client is an equal opportunity employer. We encourage you to apply even if you don’t meet every qualification—your background could be exactly what this team needs.