Senior Wafer-Level Test Architect | V93000 Expert

advantestcareers; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

Advantest seeks a Lead Application Engineer in California to join the R&V team. You will design, implement, and optimize wafer‑level test programs on the V93000 platform, focusing on thermal management and high‑performance die‑level testing.

You will lead technical discussions, collaborate with R&D and customers, and own end‑to‑end test solutions spanning hardware, probers, and software, driving innovative semiconductor testing capabilities.

Qualifications

• Bachelor’s degree or higher in EE, CE, CS or related field.
• 5–7 years of hands-on experience developing and debugging test programs on V93000 with SmarTest8.
• Proficiency in Java for test program development.
• Hands-on experience with wafer-level (die-level) testing using die-level probers.
• Experience managing thermal aspects of test devices across temperature ranges.
• Experience with V93000 hardware, load boards, probe cards, and prober integration.

Responsibilities

• Lead design, development, execution, and debugging of test programs on the Advantest V93000 platform.
• Develop test methods and reusable libraries using C++ and Java in SmarTest8.
• Own wafer-level test program development, including silicon bring‑up and characterization.
• Manage and optimize thermal aspects of device testing and correlation across temperatures.
• Develop test programs for high‑power devices that manage power dissipation during testing.
• Provide end‑to‑end ownership of test solutions spanning ATE hardware, probers, and software.

Skills

SmarTest8

Java

C++

Wafer-level testing

V93000

Thermal management

Education

Bachelor’s degree in Electrical Engineering / Computer Engineering / Computer Science

Tools

Die-level probers

Job description

Advantest seeks a Lead Application Engineer in California to join the R&V team. You will design, implement, and optimize wafer‑level test programs on the V93000 platform, focusing on thermal management and high‑performance die‑level testing.

You will lead technical discussions, collaborate with R&D and customers, and own end‑to‑end test solutions spanning hardware, probers, and software, driving innovative semiconductor testing capabilities.