Senior VLSI ECO Routing & Optimization Engineer

NVIDIA AI; Santa Clara (TX); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA is seeking a Senior Software R&D Engineer to invent the next generation of detailed physical design algorithms, focusing on ECO routing and optimization. You will work on timing and power optimization, incremental logic synthesis, metal ECOs, and high-speed interconnect, with end-to-end ownership from invention to production.

Ideal candidates have 5+ years of experience and a strong background in C++, high-performance software architecture, and detailed routing.

Qualifications

• MS, PhD or equivalent with 5+ years of relevant experience.
• Strong expertise in C++, high-performance software architecture and algorithms.
• Deep understanding of detailed routing, DRC-aware implementation.
• Knowledge of clock distribution, DFT, and power delivery.
• Authorization to work on export controlled data.

Responsibilities

• Develop incremental physical-design tech capable of rapid high-performance logic changes with DRC awareness for all-layer and metal ECOs.
• Invent improved detailed-routing algorithms for DRC-constrained manufacturing processes.
• Help craft cross-domain optimization tools considering logic, timing, clocks, testability, power and placement.
• Own problems end-to-end from invention to production deployment.

Skills

C++

Algorithms

High-performance

Detailed routing

DRC awareness

Education

MS/PhD

Job description

NVIDIA is seeking a Senior Software R&D Engineer to invent the next generation of detailed physical design algorithms, focusing on ECO routing and optimization. You will work on timing and power optimization, incremental logic synthesis, metal ECOs, and high-speed interconnect, with end-to-end ownership from invention to production.

Ideal candidates have 5+ years of experience and a strong background in C++, high-performance software architecture, and detailed routing.