Senior UVM-Based SoC Verification Engineer

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking a seasoned SoC verification engineer in the United States to create and update UVM-based test benches and test cases that align with microarchitecture specifications.

You will execute verification plans using emulation and system simulation, debug presilicon issues, and collaborate with RTL, postsilicon, and physical design teams to enhance verification coverage, infrastructure, and test plans. Documentation and thorough reviews are essential.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 4+ years in SoC design verification or Master's with 3+ years.
• Demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.
• AMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors.
• Creation and updating of UVM-based test benches and test cases.

Responsibilities

• Create and update UVM-based test benches and test case creation to reflect current microarchitecture specs.
• Define and develop scalable, reusable verification plans for blocks, subsystems, and SoCs.
• Build test environments and test benches that align with design specs and validation goals.
• Execute verification plans using emulation and system simulation models to uncover functional bugs.
• Debug root causes in presilicon environments and implement corrective actions.
• Collaborate with architects, RTL, postsilicon, and physical design teams to improve verification coverage.
• Document and maintain test plans; lead technical reviews with design and architecture teams.
• Integrate security coverage into test plans, including regression and debug tests.
• Maintain and improve verification infrastructure and methodologies; absorb learnings from postsilicon.

Skills

UVM Methodologies

SoC Verification

Debugging

Test Planning

AMBA Protocols

Education

Bachelor's degree (Electrical/Computer Engineering or CS) + 4+ years

Master's degree (Electrical/Computer Engineering or CS) + 3+ years

Tools

EDA VIPs

EDA Tools

Job description

Jobtailor is seeking a seasoned SoC verification engineer in the United States to create and update UVM-based test benches and test cases that align with microarchitecture specifications.

You will execute verification plans using emulation and system simulation, debug presilicon issues, and collaborate with RTL, postsilicon, and physical design teams to enhance verification coverage, infrastructure, and test plans. Documentation and thorough reviews are essential.