Senior TPU Performance Co-Design Engineer

Google; Sunnyvale (CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google Sunnyvale, CA invites a Senior Staff Performance Codesign Engineer to shape TPU hardware and software for world-class AI/ML workloads. You will drive architecture decisions, verify complex digital designs, and align research with production systems powering billions of user-facing services.

The role emphasizes cross‑functional leadership, performance modeling, and scalable ML pipelines, with opportunities to influence multi‑generational hardware solutions and next‑gen accelerators.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 12 years of experience in computer/chip architecture or hardware-software co-design.
• Experience with performance modeling, simulation or system analysis.

Responsibilities

• Define and drive the technical roadmap and architecture for the hardware/software stack for ML training and serving.
• Act as the technical liaison between advanced research, software, and hardware teams to maximize scaling and efficiency.
• Architect and oversee next‑generation configurable simulation frameworks and cycle‑accurate performance models.
• Advocate system‑level performance analysis across distributed ML systems and optimize compute/memory/interconnect requirements.
• Manage cross‑functional partnerships to influence strategy and production transitions.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

12 years of experience in computer architecture, chip architecture, or hardware-software co-design

Experience developing systems for performance modeling, simulation, or system analysis

Job description

Google Sunnyvale, CA invites a Senior Staff Performance Codesign Engineer to shape TPU hardware and software for world-class AI/ML workloads. You will drive architecture decisions, verify complex digital designs, and align research with production systems powering billions of user-facing services.

The role emphasizes cross‑functional leadership, performance modeling, and scalable ML pipelines, with opportunities to influence multi‑generational hardware solutions and next‑gen accelerators.