Senior TPU ML Performance Engineer

Google

United States

On-site

USD 174,000 - 252,000

Full time

14 days+

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Job summary

Google Senior Software Engineer, Fleet-level ML Performance in Sunnyvale, CA, leads fleet-level performance analysis of ML workloads on future TPU systems using advanced simulation tools to balance performance and cost. You will collaborate with model researchers, compiler developers, systems engineers, and TPU architects to optimize the design space.

The role drives architecture decisions to maximize TPU efficiency while accounting for power, reliability (RAS), and scheduling, contributing to

Qualifications

Bachelor's degree in CS, EE, CE or related field.
5 years of experience in systems or data center architecture and performance optimization.
Experience with Reliability, Availability, and Serviceability (RAS) features, paradigms, or architecture.

Responsibilities

Perform fleet-level performance analysis of key ML workloads on future TPU systems using advanced simulation tools to evaluate hardware/software trade-offs and guide next-generation chip architecture.
Partner with teams across the ML stack including model researchers, compiler developers, systems engineers, and TPU architects to analyze and optimize performance across the design space.
Design and implement a unified ML Accelerator Platform Performance Estimation Methodology using C++ and Python to enable scalable performance and TCO projections across Google.
Collaborate cross-functionally with data center, hardware architecture, and framework teams to define key hardware and software requirements for future AI infrastructure.