Senior TPU Design Engineer, Silicon

Google LLC; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a Senior TPU Design Engineer, Silicon, in Mountain View, CA. You will lead RTL design and microarchitecture for ML accelerators, drive IP/SoC development, and collaborate with hardware, software, and ML teams to deliver high-performance silicon.

The role emphasizes leadership of IP/SoC design efforts, experience with ARM-based SoCs, interconnects, and ASIC methodology, and a track record of delivering complex silicon projects on schedule. In-person interviews are typical.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8 years of experience with RTL design using Verilog/SystemVerilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Skills

RTL design

Verilog/SystemVerilog

IP/SoC design leadership

ARM-based SoCs

Interconnects

ASIC methodology

Education

Bachelor's degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

Job description

Share Senior TPU Design Engineer, Silicon

In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical/Computer Engineering, or a related field.
• 10 years of experience with IP design for Complex IPs in Machine learning, Neural Processors, Multimedia or GPUs.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience leading technical teams.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and Field-programmable Gate Array (FPGA)/silicon bring-up.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google’s EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.