Senior Test Engineer – ATE & Wafer Sort

Microchip Technology Inc.; San Jose (CA); On-site; USD 70,000 - 163,000; Full time

Benefits offered by this job

Competitive base pay

Health benefits

Retirement savings plans

Quarterly bonuses

Job summary

A leading semiconductor company is seeking a Senior Engineer I - Test in San Jose, CA. You will implement ATE test solutions and support the FPGA business unit. Ideal candidates will have a strong background in ATE test engineering, experience with semiconductor wafer sorting, and proficiency in programming languages like Visual Basic and Perl. Competitive compensation and comprehensive benefits are included.

Qualifications

• 5 years of experience with semiconductor ATE test engineering.
• Experience in wafer sort and final test development.
• Understanding of post-silicon validation and verifications.

Responsibilities

• Define and implement manufacturing test solutions for semiconductor wafer sort and final test.
• Develop test strategy to cover specification, design and qualification of silicon.
• Analyze electronics and components for failures in manufacturing.

Skills

ATE test engineering

Visual Basic

Perl programming

Communication skills

Team player

Education

Bachelor's or Master's degree in engineering

Tools

Testing hardware and equipment

Laboratory equipment

Job description

A leading semiconductor company is seeking a Senior Engineer I - Test in San Jose, CA. You will implement ATE test solutions and support the FPGA business unit. Ideal candidates will have a strong background in ATE test engineering, experience with semiconductor wafer sorting, and proficiency in programming languages like Visual Basic and Perl. Competitive compensation and comprehensive benefits are included.