Senior Technical Staff Engineer - Validation (System Design)

Microchip; California (MO); On-site; USD 70,304 - 143,000; Full time

Benefits offered by this job

Medical benefits

401K

RSU

Bonus

Job summary

Microchip Technology Inc. is seeking a Senior Technical Staff Engineer - Validation (System Design) based in San Jose, CA. Lead FPGA‑based system design validation, lab bringup, and partial reconfiguration use cases for Microchip products.

You will Architect FPGA designs, validate system level use models, and mentor engineers while collaborating across teams to ensure quality and timely delivery.

Qualifications

• Requires a BSEE/BSCS or equivalent with 15+ years of experience.
• MS seat is preferred (MSEE/MSCS)
• Strong knowledge of FPGA architectures is required.
• Deep experience in hardware design validation and lab bringup.
• Proficiency with Verilog/VHDL coding and RTL design.
• Experience with high‑speed serial interfaces and PCIe.
• Familiarity with debugging tools and lab equipment.

Responsibilities

• Lead system and FPGA design validation activities and lab bringup.
• Define and implement system‑level use models and validation plans.
• Write and maintain Verilog/VHDL code; support regression.
• Mentor engineers and collaborate across cross‑functional teams.
• Interface with India team for time‑zone collaboration.
• Apply AI tools to automate FPGA design/validation workflows.

Skills

FPGA design

Verilog/VHDL

C/C++

System level design

Lab bringup

High‑speed serial protocols

Python scripting

Debugging in lab

Education

BSEE/BSCS

MSEE/MSCS preferred

Tools

ModelSim

Synplify

Spirent Test Center

PCIe Analyzer

Job description

Senior Technical Staff Engineer - Validation (System Design)

Microchip Technology Inc. has a Senior Technical Staff Engineer - Validation (System Design) opening based in San Jose, CA. The candidate will be an expert with lab bring up and automation of FPGA design creation and validation, be able to use FPGAs to create systems level designs, and possess expertise in development of partial re‑configuration use cases. The successful candidate will be responsible for the following.

• Be an expert with use of FPGAs to create systems level designs to bring up and debug such systems in the lab, including having deep experience in validating systems level UCs for partial reconfiguration
• Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products
• System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting
• Develop high level system and product level validation plans for new and existing silicon products and projects, execute per plan, review dependencies, estimate effort and identify and communicate risk
• Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features
• Be not only an effective contributor but also the technical expert related to protocols using high speed serial interfaces in a cross‑functional team‑oriented environment
• Write high quality code in Verilog, VHDL and C code. Maintain existing code. Support regression and re‑use
• Learn new system designs and validation methodologies. Understand FPGA architectures
• Act as the authoritative expert in knowledge domain area(s), mentor senior and junior engineers and provide technical guidance, including assigning and monitoring tasks of employees and contractors
• Collaborate with cross‑functional managers/teams to identify and resolve inter‑dependencies
• Define and improve process followed in the department; follow quality metrics and assess per project
• Must be willing to take regular late night or early morning calls to interface with the engineering team in India Standard Time zone, when and if required
• Use AI based tools to automate workflows and help improve the FPGA design and validation processes

Requirements/Qualifications

• BSEE / BSCS or equivalent with 15+ years of experience
• MSEE / MSCS preferred
• Knowledge of FPGA architectures is a must
• Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
• Strong technical background in FPGA prototype emulation, and debug
• Strong technical background in silicon validation, failure analysis and debug
• Excellent board level debug capabilities in lab environment: hands‑on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
• Design with RTL coding in Verilog and VHDL is a must
• Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools
• Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB
• Familiarity with the bring up and on‑board debug of 32Gbps SERDES
• Hands‑on systems level design and debug experience with high‑speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol)
• Protocol testing at UNH for various IEEE Clauses pertaining to Layer 1/2/3 of Gigabit Ethernet
• PCIe Gen3/4/5
• Experience with the Lab Equipment: Spirent Test Center or equivalent Traffic Generators and Checkers, PCIe Analyzer & PCIe Exerciser
• Strong commitment to quality and customer satisfaction
• Excellent verbal and written communication skills in English
• Able to travel 0-2 times annually if required
• C, C++ or object‑oriented programming skills are required
• Knowledge and experience in embedded firmware development
• Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable
• Experience with Python/PERL/TCL scripting

Preferred qualifications

• Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA: Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMII
• Interlaken (4.25 to 412.5 Gbps)
• OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
• (E,X,XGS,NG)-PON or 100G-EPON
• Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), DisplayPort (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
• JESD204C (6.375 to 32 Gbps)

Design and debug experience for any of the below high‑speed serial communications protocols is a plus, but not necessary:

• Hybrid Memory Cube
• CPRI Rate 1 to 10+
• Serial Rapid IO 4.1
• USB 3.0
• SATA I, II, III
• Fiber Channel
• CoaXpress

Percentage of time spent

• Documentation – 15%
• Design Creation & Verification – 25%
• Lab Bringup & Debug – 60%

Essential Physical Functions and Working Conditions

• 50 % work in front of computer
• 50% work in the lab

Benefits

• Wellness & Medical Benefits effective on your First Day of Employment
• Gold Standard in Medical, Prescription Drug, Dental & Vision Benefits
• Quarterly Employee Cash Bonus Plan
• Restricted Stock Grant
• Employee Stock Purchase Plan
• Tuition Reimbursement
• 401K Retirement Savings Plan
• Spending Accounts
• Life Insurance
• Long Term Care
• Legal
• Employee Assistance Plan

Paid Time Off

• Vacation Pay
• Absence Time - Sick Pay
• 10 Paid Holidays

Travel Time

0% - 25%

Physical Attributes

• Carrying, Feeling, Handling, Hearing, Other, Reaching, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements

70% sitting; 15% walking; 15% standing; 100% in doors; Usual business hours

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Equal Employment Opportunity Statement

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.